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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC] f16 inline constants are still enabled for integer operands of several opcodes"
href="https://bugs.llvm.org/show_bug.cgi?id=46980">46980</a>
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<th>Summary</th>
<td>[AMDGPU][MC] f16 inline constants are still enabled for integer operands of several opcodes
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>A recent change 5f5f566 disabled use of fp inline constants with 16-bit integer
operands. However there are several opcodes which still accept such constants:
s_sext_i32_i16
s_pack_lh_b32_b16
s_pack_ll_b32_b16
s_pack_hh_b32_b16
v_sat_pk_u8_i16
v_sad_u16
I believe this should be corrected.
Also there are opcodes which operate with 8-bit and 4-bit data, for example,
s_sext_i32_i8. Should fp inline constants be disabled for these instructions?
qsad opcodes (v_mqsad_pk_u16_u8, v_qsad_pk_u16_u8 etc) is another interesting
case because these instructions accept u16x4 operands; it is not clear how fp
inline constants are interpreted in this context.
Any ideas?</pre>
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