[llvm-bugs] [Bug 46971] New: AArch64 assembler does not support pseudo instruction LDR q0, =<128-bit value>

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46971

            Bug ID: 46971
           Summary: AArch64 assembler does not support pseudo instruction
                    LDR q0,=<128-bit value>
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: smithp352 at googlemail.com
                CC: arnaud.degrandmaison at arm.com,
                    llvm-bugs at lists.llvm.org, smithp352 at googlemail.com,
                    Ties.Stuij at arm.com

LLVM supports this pseudo instruction for S and X registers (32 and 64-bit)
instructions, but it does not support Q registers.

For example:
 .text
 ldr q0,=0x123456781234567812345678

clang --target=aarch64-linux-gnu ldrtest.s
ldr_test.s:2:10: error: literal value out of range for directive
 ldr q0,=0x123456781234567812345678

GCC does support this pseudo instruction, translating it to
0x0 ldr q0, <$d>
...
<$d>
0x10 .word 0x12345678
0x14 .word 0x12345678
0x18 .word 0x12345678
0x1c .word 0x00000000

As a pseudo instruction without a specification of what registers it should
handle; I don't think that this is a critical problem, but it would be nice to
have parity between GCC and LLVM.

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