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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - AArch64 assembler does not support pseudo instruction LDR q0,=<128-bit value>"
href="https://bugs.llvm.org/show_bug.cgi?id=46971">46971</a>
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<th>Summary</th>
<td>AArch64 assembler does not support pseudo instruction LDR q0,=<128-bit value>
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AArch64
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>smithp352@googlemail.com
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<th>CC</th>
<td>arnaud.degrandmaison@arm.com, llvm-bugs@lists.llvm.org, smithp352@googlemail.com, Ties.Stuij@arm.com
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<p>
<div>
<pre>LLVM supports this pseudo instruction for S and X registers (32 and 64-bit)
instructions, but it does not support Q registers.
For example:
.text
ldr q0,=0x123456781234567812345678
clang --target=aarch64-linux-gnu ldrtest.s
ldr_test.s:2:10: error: literal value out of range for directive
ldr q0,=0x123456781234567812345678
GCC does support this pseudo instruction, translating it to
0x0 ldr q0, <$d>
...
<$d>
0x10 .word 0x12345678
0x14 .word 0x12345678
0x18 .word 0x12345678
0x1c .word 0x00000000
As a pseudo instruction without a specification of what registers it should
handle; I don't think that this is a critical problem, but it would be nice to
have parity between GCC and LLVM.</pre>
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