[llvm-bugs] [Bug 45705] New: [arm] Merge 8807139026b6 into 10.0.1

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=45705

            Bug ID: 45705
           Summary: [arm] Merge 8807139026b6 into 10.0.1
           Product: new-bugs
           Version: 10.0
          Hardware: Other
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: dimitry at andric.com
                CC: htmldeveloper at gmail.com, llvm-bugs at lists.llvm.org

Please merge
https://reviews.llvm.org/rG8807139026b64ac40163bb255dad38a1d8054f08 into
10.0.1. This fixes bug 45677, a fatal backend error when targeting armv5:

Author: David Green
Date: 2020-04-27T10:13:29+01:00
New Revision: 8807139026b64ac40163bb255dad38a1d8054f08

URL:
https://github.com/llvm/llvm-project/commit/8807139026b64ac40163bb255dad38a1d8054f08
DIFF:
https://github.com/llvm/llvm-project/commit/8807139026b64ac40163bb255dad38a1d8054f08.diff

LOG: [ARM] Only produce qadd8b under hasV6Ops

When compiling for a arm5te cpu from clang, the +dsp attribute is set.
This meant we could try and generate qadd8 instructions where we would
end up having no pattern. I've changed the condition here to be hasV6Ops
&& hasDSP, which is what other parts of ARMISelLowering seem to use for
similar instructions.

Fixed PR45677.

Differential Revision: https://reviews.llvm.org/D78877

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