[llvm-bugs] [Bug 43365] New: Merge r372186 and r372187 to 9.0 branch: [ARM] VFPv2 only supports 16 D registers.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=43365

            Bug ID: 43365
           Summary: Merge r372186 and r372187 to 9.0 branch: [ARM] VFPv2
                    only supports 16 D registers.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: efriedma at quicinc.com
                CC: llvm-bugs at lists.llvm.org, oliver.stannard at arm.com,
                    peter.smith at linaro.org, t.p.northover at gmail.com,
                    Ties.Stuij at arm.com

These fix a very easy to reproduce miscompile if the user specifies -mfpu=vfpv2
(or an equivalent -mcpu flag).  Probably not that important for general usage,
since it only affects pre-v7 ARM targets with an FPU, but it's a showstopper if
you need to target one of those specific CPUs.

Should be low risk in terms of correctness, but I'm not sure whether we're
allowed to remove target features in a point release.  Maybe on the branch we
could keep the "vfp2d16" and "vfp2d16sp" target features, but make them no-ops.

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