[llvm-bugs] [Bug 44038] New: [MSP430][AVR][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (1/8)

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https://bugs.llvm.org/show_bug.cgi?id=44038

            Bug ID: 44038
           Summary: [MSP430][AVR][InstCombine][DAGCombine]Poor codegen for
                    targets with no native shifts (1/8)
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: joan.lluch at icloud.com
                CC: llvm-bugs at lists.llvm.org

A number of comparisons involving bit tests are converted into shifts by
InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit
targets with comparatively cheaper selects. 

It is desirable that selects are emitted instead of shifts for these targets.
The following cases were identified in TargetLowering and DAGCombine and were
fixed by:

https://reviews.llvm.org/D69116 
https://reviews.llvm.org/D69120
https://reviews.llvm.org/D69326
https://reviews.llvm.org/D70042

Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that
these cases should be fixed by reversing the current canonicalisation. I am
showing them in this and following reports:

REPORTED CASE:

Source code:

int testSimplifySetCC_0( int x )  // (InstCombineCasts::transformZExtICmp)
{
  return (x & 32) != 0;
}

IR code:

define i16 @testSimplifySetCC_0(i16 %x) {
entry:
  %and = lshr i16 %x, 5
  %and.lobit = and i16 %and, 1
  ret i16 %and.lobit
}

MSP430 Target code:

testSimplifySetCC_0:
        clrc
        rrc     r12
        rra     r12
        rra     r12
        rra     r12
        rra     r12
        and     #1, r12
        ret

AVR Target code:

testSimplifySetCC_0:
        lsr     r25
        ror     r24
        lsr     r25
        ror     r24
        lsr     r25
        ror     r24
        lsr     r25
        ror     r24
        lsr     r25
        ror     r24
        andi    r24, 1
        andi    r25, 0
        ret


EXPECTED RESULT:

Source code:

int testSimplifySetCC_0( int x )  // (InstCombineCasts::transformZExtICmp)
{
  return (x & 32) != 0;
}

Expected IR code:

define dso_local i16 @testSimplifySetCC_0(i16 %x) local_unnamed_addr #0 {
entry:
  %and = and i16 %x, 32
  %cmp = icmp ne i16 %and, 0
  %conv = zext i1 %cmp to i16
  ret i16 %conv
}


Expected MSP430 Target code: 

testSimplifySetCC_0:
        bit     #32, r12
        mov     r2, r12
        and     #1, r12
        ret


Expected AVR Target code:

testSimplifySetCC_0:
        andi    r24, 32
        andi    r25, 0
        ldi     r20, 0
        ldi     r21, 0
        ldi     r18, 1
        cp      r24, r20
        cpc     r25, r21
        brne    LBB0_2
        ldi     r18, 0
LBB0_2:
        mov     r24, r18
        clr     r25
        ret

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