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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [MSP430][AVR][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (1/8)"
href="https://bugs.llvm.org/show_bug.cgi?id=44038">44038</a>
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<th>Summary</th>
<td>[MSP430][AVR][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (1/8)
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Common Code Generator Code
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>joan.lluch@icloud.com
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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</tr></table>
<p>
<div>
<pre>A number of comparisons involving bit tests are converted into shifts by
InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit
targets with comparatively cheaper selects.
It is desirable that selects are emitted instead of shifts for these targets.
The following cases were identified in TargetLowering and DAGCombine and were
fixed by:
<a href="https://reviews.llvm.org/D69116">https://reviews.llvm.org/D69116</a>
<a href="https://reviews.llvm.org/D69120">https://reviews.llvm.org/D69120</a>
<a href="https://reviews.llvm.org/D69326">https://reviews.llvm.org/D69326</a>
<a href="https://reviews.llvm.org/D70042">https://reviews.llvm.org/D70042</a>
Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that
these cases should be fixed by reversing the current canonicalisation. I am
showing them in this and following reports:
REPORTED CASE:
Source code:
int testSimplifySetCC_0( int x ) // (InstCombineCasts::transformZExtICmp)
{
return (x & 32) != 0;
}
IR code:
define i16 @testSimplifySetCC_0(i16 %x) {
entry:
%and = lshr i16 %x, 5
%and.lobit = and i16 %and, 1
ret i16 %and.lobit
}
MSP430 Target code:
testSimplifySetCC_0:
clrc
rrc r12
rra r12
rra r12
rra r12
rra r12
and #1, r12
ret
AVR Target code:
testSimplifySetCC_0:
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
andi r24, 1
andi r25, 0
ret
EXPECTED RESULT:
Source code:
int testSimplifySetCC_0( int x ) // (InstCombineCasts::transformZExtICmp)
{
return (x & 32) != 0;
}
Expected IR code:
define dso_local i16 @testSimplifySetCC_0(i16 %x) local_unnamed_addr #0 {
entry:
%and = and i16 %x, 32
%cmp = icmp ne i16 %and, 0
%conv = zext i1 %cmp to i16
ret i16 %conv
}
Expected MSP430 Target code:
testSimplifySetCC_0:
bit #32, r12
mov r2, r12
and #1, r12
ret
Expected AVR Target code:
testSimplifySetCC_0:
andi r24, 32
andi r25, 0
ldi r20, 0
ldi r21, 0
ldi r18, 1
cp r24, r20
cpc r25, r21
brne LBB0_2
ldi r18, 0
LBB0_2:
mov r24, r18
clr r25
ret</pre>
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