[llvm-bugs] [Bug 41790] New: When same reg is used for output and implicit-def, spill is inserted and overwrites output result

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=41790

            Bug ID: 41790
           Summary: When same reg is used for output and implicit-def,
                    spill is inserted and overwrites output result
           Product: libraries
           Version: 7.0
          Hardware: Other
                OS: other
            Status: NEW
          Severity: normal
          Priority: P
         Component: Register Allocator
          Assignee: unassignedbugs at nondot.org
          Reporter: code.kchoi at gmail.com
                CC: llvm-bugs at lists.llvm.org, quentin.colombet at gmail.com

(Paste from @llvm.dev) I ran into a case where RegAlloc would insert a spill
across instruction that had same register for output operand and implicit-def.
The effect this had was that spill code would immediately overwrite the output
result. Is this the expected result of setting up MyInst this way? In other
words, does RegAlloc know to not insert spill in case it sees that output reg
is same as one of implicit-def?

If this is intended (always spilling live regs across implicit-def inst?), I am
puzzled on how to use MyInst that has variable output reg with static
implicit-defs. Any tips would be greatly appreciated.

Reduced Example:
Before RegAlloc:
%1:reg = COPY ...;
%2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;
%3:reg = Use %2:reg

RegAlloc:
>> %2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;
Regs: $p1=%1
Killing last use: %1:reg
Assigning %2 to $p1
Spilling %2 in $p1 to stack slot #2  <-- suspicious if this is inserting spill,
unaware of output reg being same
<< $p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;

After RegAlloc:
$p1 = COPY ...;
Store $p1 %stack.2;
$p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;
$p1 = Load %stack.2;
$p2 = Use $p1, ...;

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