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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - When same reg is used for output and implicit-def, spill is inserted and overwrites output result"
href="https://bugs.llvm.org/show_bug.cgi?id=41790">41790</a>
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<th>Summary</th>
<td>When same reg is used for output and implicit-def, spill is inserted and overwrites output result
</td>
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>7.0
</td>
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<th>Hardware</th>
<td>Other
</td>
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<th>OS</th>
<td>other
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Register Allocator
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>code.kchoi@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org, quentin.colombet@gmail.com
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<pre>(Paste from @llvm.dev) I ran into a case where RegAlloc would insert a spill
across instruction that had same register for output operand and implicit-def.
The effect this had was that spill code would immediately overwrite the output
result. Is this the expected result of setting up MyInst this way? In other
words, does RegAlloc know to not insert spill in case it sees that output reg
is same as one of implicit-def?
If this is intended (always spilling live regs across implicit-def inst?), I am
puzzled on how to use MyInst that has variable output reg with static
implicit-defs. Any tips would be greatly appreciated.
Reduced Example:
Before RegAlloc:
%1:reg = COPY ...;
%2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;
%3:reg = Use %2:reg
RegAlloc:
<span class="quote">>> %2:reg = MyInst %1:reg, ..., implicit-def dead $p1, ...;</span >
Regs: $p1=%1
Killing last use: %1:reg
Assigning %2 to $p1
Spilling %2 in $p1 to stack slot #2 <-- suspicious if this is inserting spill,
unaware of output reg being same
<< $p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;
After RegAlloc:
$p1 = COPY ...;
Store $p1 %stack.2;
$p1 =MyInst killed $p1, ..., implicit-def dead $p1, ...;
$p1 = Load %stack.2;
$p2 = Use $p1, ...;</pre>
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