[llvm-bugs] [Bug 41028] New: Instructions for NVPTX backends are improperly swapped in optimization passes

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=41028

            Bug ID: 41028
           Summary: Instructions for NVPTX backends are improperly swapped
                    in optimization passes
           Product: tools
           Version: 7.0
          Hardware: All
                OS: Linux
            Status: NEW
          Severity: release blocker
          Priority: P
         Component: opt
          Assignee: unassignedbugs at nondot.org
          Reporter: linearhit at foxmail.com
                CC: llvm-bugs at lists.llvm.org

The nvvm.barrier0 intrinsic is for _sync_threads of the NVPTX backend. It
cannot be swapped with store/load instructions toward the GPU shared memory,
(aka, store/load toward addressspace(3) in the IR). From the IRs before/after
llvm optimization passes, it seems that the order of the instructions are
improperly optimized, which further causes some severe correctness issue.

The issue was found during some work on Tensorflow XLA, currently I don't know
which llvm optimization pass causes the issue.

IRs before optimization passes: (pay attention to line 42 and line 69)

IRs after optimization passes: (pay attention to line 19 and line 45)

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