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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Instructions for NVPTX backends are improperly swapped in optimization passes"
href="https://bugs.llvm.org/show_bug.cgi?id=41028">41028</a>
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<th>Summary</th>
<td>Instructions for NVPTX backends are improperly swapped in optimization passes
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>7.0
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>Linux
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>release blocker
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>opt
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>linearhit@foxmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<p>
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<pre>The nvvm.barrier0 intrinsic is for _sync_threads of the NVPTX backend. It
cannot be swapped with store/load instructions toward the GPU shared memory,
(aka, store/load toward addressspace(3) in the IR). From the IRs before/after
llvm optimization passes, it seems that the order of the instructions are
improperly optimized, which further causes some severe correctness issue.
The issue was found during some work on Tensorflow XLA, currently I don't know
which llvm optimization pass causes the issue.
IRs before optimization passes: (pay attention to line 42 and line 69)
IRs after optimization passes: (pay attention to line 19 and line 45)</pre>
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