[llvm-bugs] [Bug 41023] New: [AArch64] Use UQADD for vector UADDSAT etc

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https://bugs.llvm.org/show_bug.cgi?id=41023

            Bug ID: 41023
           Summary: [AArch64] Use UQADD for vector UADDSAT etc
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: nikita.ppv at gmail.com
                CC: arnaud.degrandmaison at arm.com,
                    llvm-bugs at lists.llvm.org, peter.smith at linaro.org,
                    Ties.Stuij at arm.com

AArch64 has uqadd, sqadd, uqsub and sqsub instructions for the legal vector
types. We should use them for uaddsat, saddsat, usubsat and ssubsat instead of
the fallback expansions.

I've tried implementing this myself, but couldn't figure out the right way to
do it. I initially thought we can just autoupgrade the aarch64.neon.uqadd etc
intrinsics to use the generic uadd.sat intrinsics instead and adjust the isel
patterns accordingly.

Unfortunately, this is complicated by the existence of the SIMD scalar variants
of these instructions. I'm assuming that it is preferable to use the fallback
expansion in the scalar case (e.g. adds+csinv) rather than using the SIMD
instruction with three register moves. On the other hand, we probably still
need to force the use of the SIMD instructions if the NEON intrinsics are used.

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