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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AArch64] Use UQADD for vector UADDSAT etc"
href="https://bugs.llvm.org/show_bug.cgi?id=41023">41023</a>
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<th>Summary</th>
<td>[AArch64] Use UQADD for vector UADDSAT etc
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AArch64
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>nikita.ppv@gmail.com
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<th>CC</th>
<td>arnaud.degrandmaison@arm.com, llvm-bugs@lists.llvm.org, peter.smith@linaro.org, Ties.Stuij@arm.com
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<pre>AArch64 has uqadd, sqadd, uqsub and sqsub instructions for the legal vector
types. We should use them for uaddsat, saddsat, usubsat and ssubsat instead of
the fallback expansions.
I've tried implementing this myself, but couldn't figure out the right way to
do it. I initially thought we can just autoupgrade the aarch64.neon.uqadd etc
intrinsics to use the generic uadd.sat intrinsics instead and adjust the isel
patterns accordingly.
Unfortunately, this is complicated by the existence of the SIMD scalar variants
of these instructions. I'm assuming that it is preferable to use the fallback
expansion in the scalar case (e.g. adds+csinv) rather than using the SIMD
instruction with three register moves. On the other hand, we probably still
need to force the use of the SIMD instructions if the NEON intrinsics are used.</pre>
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