[llvm-bugs] [Bug 42307] New: [mca] Multiple reservation station handling

via llvm-bugs llvm-bugs at lists.llvm.org
Tue Jun 18 09:40:01 PDT 2019


            Bug ID: 42307
           Summary: [mca] Multiple reservation station handling
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llvm-mca
          Assignee: unassignedbugs at nondot.org
          Reporter: lebedev.ri at gmail.com
                CC: andrea.dibiagio at gmail.com, llvm-bugs at lists.llvm.org,
                    matthew.davis at sony.com

Created attachment 22119
  --> https://bugs.llvm.org/attachment.cgi?id=22119&action=edit

Currently llvm-mca *seems* to only handle the case when there
is a single reservation station for a number of execution pipes.

That is more or less isn't the case for for -mcpu=amdfam10h
* AMD Software Optimization Guide for AMD Family 10h and 12h Processors
  Appendix A Microarchitecture of AMD Family 10h and 12h Processors
* https://www.realworldtech.com/barcelona/ 
* I think this is more or less stated as such in Agner, but not specifically

Bach of 6 pipes (3 integer, 3 fp) has it's own scheduler with it's own
reservation station.
But as you can see from test/tools/llvm-mca/X86/scheduler-queue-usage.s
it seems, MCA only currently recognizes this:

def BnInt : ProcResGroup<[BnInt0, BnInt1, BnInt2]> {
  let BufferSize = 24;

^ only BnInt queue ever is being used.

A simple 
  def BnI0 : ProcResGroup<[BnInt0]> {
    let BufferSize = 24;

isn't recognized, neither is

  def BnInt0 : ProcResource<1> {
    let BufferSize = 8;

Am i missing something truly obvious here?

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