[llvm-bugs] [Bug 40881] New: [SelectionDAG] Create ZEXTLOAD over EXTLOAD if its going to be lowered to that anyway

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=40881

            Bug ID: 40881
           Summary: [SelectionDAG] Create ZEXTLOAD over EXTLOAD if its
                    going to be lowered to that anyway
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: efriedma at quicinc.com, llvm-bugs at lists.llvm.org,
                    spatel+llvm at rotateright.com

The aarch64 regression in D58017 is due to the load+zext being combined to a
EXTLOAD instead of a ZEXTLOAD as the upper bits are not required -
SimplifyDemandedBits reduces the zext to an aext before the load+zext are
combined.

This is actually a common issue - many targets will always lower an EXTLOAD to
ZEXTLOAD anyway so we might as well use ZEXTLOAD earlier which allows other
combines to then make use of the certainty that the upper bits will be zero.

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