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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [SelectionDAG] Create ZEXTLOAD over EXTLOAD if its going to be lowered to that anyway"
href="https://bugs.llvm.org/show_bug.cgi?id=40881">40881</a>
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<th>Summary</th>
<td>[SelectionDAG] Create ZEXTLOAD over EXTLOAD if its going to be lowered to that anyway
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Common Code Generator Code
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
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<th>CC</th>
<td>efriedma@quicinc.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
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<pre>The aarch64 regression in D58017 is due to the load+zext being combined to a
EXTLOAD instead of a ZEXTLOAD as the upper bits are not required -
SimplifyDemandedBits reduces the zext to an aext before the load+zext are
combined.
This is actually a common issue - many targets will always lower an EXTLOAD to
ZEXTLOAD anyway so we might as well use ZEXTLOAD earlier which allows other
combines to then make use of the certainty that the upper bits will be zero.</pre>
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