[llvm-bugs] [Bug 40830] New: [X86] Avoid RMW ADC/SBB operations on some targets

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=40830

            Bug ID: 40830
           Summary: [X86] Avoid RMW ADC/SBB operations on some targets
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: andrea.dibiagio at gmail.com, craig.topper at gmail.com,
                    llvm-bugs at lists.llvm.org, llvm-dev at redking.me.uk,
                    peter at cordes.ca, spatel+llvm at rotateright.com

As discussed on [Bug #34292], some targets have particularly slow RMW
instructions and we should be avoiding their generation.

e.g. https://godbolt.org/z/YHDQPO shows that ADC/SBB RMW on Skylake is much
slower, with a higher uop count, than using folded loads and separate stores
instead, despite the latter having a higher instruction count.

On other targets, btver2 for instance, the RMW is a better option, as it
doesn't appear to generate extra uops and the weaker frontend means that a
higher instruction count will impact performance much more.

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