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      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [X86] Avoid RMW ADC/SBB operations on some targets"
   href="https://bugs.llvm.org/show_bug.cgi?id=40830">40830</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[X86] Avoid RMW ADC/SBB operations on some targets
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>llvm-dev@redking.me.uk
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>andrea.dibiagio@gmail.com, craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, peter@cordes.ca, spatel+llvm@rotateright.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>As discussed on [<a class="bz_bug_link 
          bz_status_CONFIRMED "
   title="CONFIRMED - Unusual code generation for addcarryx (ADCX and ADOX)"
   href="show_bug.cgi?id=34292">Bug #34292</a>], some targets have particularly slow RMW
instructions and we should be avoiding their generation.

e.g. <a href="https://godbolt.org/z/YHDQPO">https://godbolt.org/z/YHDQPO</a> shows that ADC/SBB RMW on Skylake is much
slower, with a higher uop count, than using folded loads and separate stores
instead, despite the latter having a higher instruction count.

On other targets, btver2 for instance, the RMW is a better option, as it
doesn't appear to generate extra uops and the weaker frontend means that a
higher instruction count will impact performance much more.</pre>
        </div>
      </p>


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