[llvm-bugs] [Bug 40690] New: Regression from llvm-6: llvm-7 replaces 'undef' with 'NaN', and generates NaN at the assembler level.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=40690

            Bug ID: 40690
           Summary: Regression from llvm-6: llvm-7 replaces 'undef' with
                    'NaN', and generates NaN at the assembler level.
           Product: libraries
           Version: 7.0
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: patrick9876 at free.fr
                CC: llvm-bugs at lists.llvm.org

This issue is a regression for mesa / radeonsi; Indeed, this generation of NaN
at the assembler level yield to some fragments shader displaying a black
screen. For instance, these two fragments shader display this faulty behavior:
https://www.shadertoy.com/view/ltl3WS and https://www.shadertoy.com/view/MdVcRd
This issue is related mainly to commit:
fc21165c2319cc584f221c7deffeeff28cbe46d3 and
2f6b67546d390b7aaf74d6eb2e349dc79318b2ee by Sanjay Patel
spatel at rotateright.com.

Here are the differences of code generation without these two commits and with,
for the first fragment shader:
18,21c18,21
<   %TEMP2.w.0 = phi float [ fmul (float fadd (float undef, float
1.000000e+00), float fmul (float 1.000000e+00, float fdiv (float 1.000000e+00,
float fadd (float undef, float 1.000000e+00)))), %main_body ], [ %170, %endif13
]
<   %TEMP2.z.0 = phi float [ fmul (float fadd (float undef, float
1.000000e+00), float fmul (float 1.000000e+00, float fdiv (float 1.000000e+00,
float fadd (float undef, float 1.000000e+00)))), %main_body ], [ %169, %endif13
]
<   %TEMP2.y.0 = phi float [ fmul (float fadd (float undef, float
1.000000e+00), float fmul (float 1.000000e+00, float fdiv (float 1.000000e+00,
float fadd (float undef, float 1.000000e+00)))), %main_body ], [ %168, %endif13
]
<   %TEMP2.x.0 = phi float [ fmul (float fadd (float undef, float
1.000000e+00), float fmul (float 1.000000e+00, float fdiv (float 1.000000e+00,
float fadd (float undef, float 1.000000e+00)))), %main_body ], [ %167, %endif13
]
---
>   %TEMP2.w.0 = phi float [ 0x7FF8000000000000, %main_body ], [ %phitmp, %endif13 ]
>   %TEMP2.z.0 = phi float [ 0x7FF8000000000000, %main_body ], [ %169, %endif13 ]
>   %TEMP2.y.0 = phi float [ 0x7FF8000000000000, %main_body ], [ %168, %endif13 ]
>   %TEMP2.x.0 = phi float [ 0x7FF8000000000000, %main_body ], [ %167, %endif13 ]
168a169
>   %phitmp = fmul nsz float %170, 0x3F50624DE0000000
175,183c176,183
<   %175 = fmul nsz float %TEMP2.w.0, 0x3F50624DE0000000
<   %176 = bitcast float %4 to i32
<   %177 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
undef, i32 %176, 4
<   %178 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
%177, float %172, 5
<   %179 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
%178, float %173, 6
<   %180 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
%179, float %174, 7
<   %181 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
%180, float %175, 8
<   %182 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
%181, float %20, 19
<   ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float,
float, float, float, float, float, float, float, float, float }> %182
---
>   %175 = bitcast float %4 to i32
>   %176 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %175, 4
>   %177 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %176, float %172, 5
>   %178 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %177, float %173, 6
>   %179 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %178, float %174, 7
>   %180 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %179, float %TEMP2.w.0, 8
>   %181 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %180, float %20, 19
>   ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %181


The issue is mainly the generation of the ‘NaN’ at the code level. This is an
aggressive simplification, and the generated ‘NaN’ must be removed. A stage
replacing again the ‘NaN’ with ‘undef’ is likely required. What do you think?

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