[llvm-bugs] [Bug 36669] New: [llvm-mca][x86] Teach how to identify instructions that perform partial register updates.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36669

            Bug ID: 36669
           Summary: [llvm-mca][x86] Teach how to identify instructions
                    that perform partial register updates.
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: llvm-bugs at lists.llvm.org

On x86-64, a 32-bit write of a GPR updates the full 64-bit register.
Example:
   add %edi, %eax   ## eax += edi

Here %eax aliases the lower half of register %rax. On x86-64, the ADD updates
the full %rax. In particular, the upper half of %rax is zeroed.

On the other hand, 8/16 bit register writes are partial register updates.
Example:
   add %di, %ax    ## ax += di

Here, register %eax is only partially updated. The lower half of %eax contains
the result of the ADD. However, the upper half of %eax is unmodified. This
means, on x86-64, only the lower 16-bit of %rax are modified; the rest of %rax
is unmodified.

Similarly, legacy SSE instructions executed on a CPU that features AVX only
partially update the aliasing super-registers.

We want to expose this information to llvm-mca, since the lack of knowledge
about partial register updates negatively impacts the the accuracy of the
performance report.

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