[llvm-bugs] [Bug 36668] New: [llvm-mca] Teach how to identify serializing instructions.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36668

            Bug ID: 36668
           Summary: [llvm-mca] Teach how to identify serializing
                    instructions.
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: llvm-bugs at lists.llvm.org

Similar to bug 36667.
However, serializing operations block the Backend until all the are no other
instructions in-flight. Essentially, these instructions block the Dispatch, and
force all the in-flight instructions to complete before new instructions are
dispatched.

This could be fixed by using an extra flag in MCInstrDesc.
In llvm-mca, this requires a few changes in the Backend/DispatchUnit logic. At
the moment, the tool doesn't know about serializing instructions.

Examples of non-privileged serializing instructions on X86 are:
CPUID, IRET

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