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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [llvm-mca][x86] Teach how to identify instructions that perform partial register updates."
href="https://bugs.llvm.org/show_bug.cgi?id=36669">36669</a>
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<th>Summary</th>
<td>[llvm-mca][x86] Teach how to identify instructions that perform partial register updates.
</td>
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<th>Product</th>
<td>new-bugs
</td>
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<th>Version</th>
<td>unspecified
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>andrea.dibiagio@gmail.com
</td>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>On x86-64, a 32-bit write of a GPR updates the full 64-bit register.
Example:
add %edi, %eax ## eax += edi
Here %eax aliases the lower half of register %rax. On x86-64, the ADD updates
the full %rax. In particular, the upper half of %rax is zeroed.
On the other hand, 8/16 bit register writes are partial register updates.
Example:
add %di, %ax ## ax += di
Here, register %eax is only partially updated. The lower half of %eax contains
the result of the ADD. However, the upper half of %eax is unmodified. This
means, on x86-64, only the lower 16-bit of %rax are modified; the rest of %rax
is unmodified.
Similarly, legacy SSE instructions executed on a CPU that features AVX only
partially update the aliasing super-registers.
We want to expose this information to llvm-mca, since the lack of knowledge
about partial register updates negatively impacts the the accuracy of the
performance report.</pre>
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