<html>
    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [llvm-mca][x86] Teach how to identify instructions that perform partial register updates."
   href="https://bugs.llvm.org/show_bug.cgi?id=36669">36669</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[llvm-mca][x86] Teach how to identify instructions that perform partial register updates.
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>new-bugs
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>new bugs
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>andrea.dibiagio@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>On x86-64, a 32-bit write of a GPR updates the full 64-bit register.
Example:
   add %edi, %eax   ## eax += edi

Here %eax aliases the lower half of register %rax. On x86-64, the ADD updates
the full %rax. In particular, the upper half of %rax is zeroed.

On the other hand, 8/16 bit register writes are partial register updates.
Example:
   add %di, %ax    ## ax += di

Here, register %eax is only partially updated. The lower half of %eax contains
the result of the ADD. However, the upper half of %eax is unmodified. This
means, on x86-64, only the lower 16-bit of %rax are modified; the rest of %rax
is unmodified.

Similarly, legacy SSE instructions executed on a CPU that features AVX only
partially update the aliasing super-registers.

We want to expose this information to llvm-mca, since the lack of knowledge
about partial register updates negatively impacts the the accuracy of the
performance report.</pre>
        </div>
      </p>


      <hr>
      <span>You are receiving this mail because:</span>

      <ul>
          <li>You are on the CC list for the bug.</li>
      </ul>
    </body>
</html>