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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [llvm-mca] Teach how to identify serializing instructions."
href="https://bugs.llvm.org/show_bug.cgi?id=36668">36668</a>
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<th>Summary</th>
<td>[llvm-mca] Teach how to identify serializing instructions.
</td>
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<th>Product</th>
<td>new-bugs
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<th>Version</th>
<td>unspecified
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>andrea.dibiagio@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>Similar to <a class="bz_bug_link
bz_status_NEW "
title="NEW - [llvm-mca] Teach the tool how to identify memory fence instructions."
href="show_bug.cgi?id=36667">bug 36667</a>.
However, serializing operations block the Backend until all the are no other
instructions in-flight. Essentially, these instructions block the Dispatch, and
force all the in-flight instructions to complete before new instructions are
dispatched.
This could be fixed by using an extra flag in MCInstrDesc.
In llvm-mca, this requires a few changes in the Backend/DispatchUnit logic. At
the moment, the tool doesn't know about serializing instructions.
Examples of non-privileged serializing instructions on X86 are:
CPUID, IRET</pre>
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