[LLVMbugs] [Bug 24192] New: Register allocation hints should understand sub registers

[bugzilla-daemon at llvm.org]

https://llvm.org/bugs/show_bug.cgi?id=24192

            Bug ID: 24192
           Summary: Register allocation hints should understand sub
                    registers
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Register Allocator
          Assignee: unassignedbugs at nondot.org
          Reporter: Matthew.Arsenault at amd.com
                CC: llvmbugs at cs.uiuc.edu, matze at braunis.de,
                    qcolombet at apple.com
    Classification: Unclassified

I'm trying to use MachineRegisterInfo::setRegAllocationHint to prefer that some
add instructions have the same source and dest register so that they can be
replaced with a += immediate add instruction. This mostly works, but doesn't
really work well for vectors.

define void @s_addk_v4i32_k0(<4 x i32> addrspace(1)* %out, <4 x i32> %b) {
  %add = add <4 x i32> %b, <i32 65, i32 66, i32 67, i32 68>
  store <4 x i32> %add, <4 x i32> addrspace(1)* %out
  ret void
}


In this case, I want to hint that the destination and source registers are the
same. For the vector case, the destination register is a 4 component super
register. The source registers are 32-bit virtual registers. There isn't a way
to hint that the 32-bit vreg source register should be allocated to the
physical sub register of the destination.


        Live Ins: %SGPR0_SGPR1
16B        %vreg0<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg0
32B        %vreg8:sub0_sub1<def,read-undef> = S_LOAD_DWORDX2_IMM %vreg0, 9;
mem:LD8[undef(addrspace=2)](nontemporal)(invariant) SReg_128:%vreg8
SReg_64:%vreg0
48B        %vreg3<def> = S_LOAD_DWORDX4_IMM %vreg0, 13;
mem:LD16[undef(addrspace=2)](nontemporal)(invariant) SReg_128:%vreg3
SReg_64:%vreg0
96B        %vreg8:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg8
112B        %vreg8:sub2<def> = S_MOV_B32 -1; SReg_128:%vreg8
304B        %vreg20<def> = S_ADD_I32 %vreg3:sub0, 65, %SCC<imp-def,dead>;
SReg_32:%vreg20 SReg_128:%vreg3
312B        %vreg17<def> = S_ADD_I32 %vreg3:sub1, 66, %SCC<imp-def,dead>;
SReg_32:%vreg17 SReg_128:%vreg3
320B        %vreg21:sub0<def,read-undef> = COPY %vreg20; VReg_128:%vreg21
SReg_32:%vreg20
336B        %vreg21:sub1<def> = COPY %vreg17; VReg_128:%vreg21 SReg_32:%vreg17
340B        %vreg14<def> = S_ADD_I32 %vreg3:sub2, 67, %SCC<imp-def,dead>;
SReg_32:%vreg14 SReg_128:%vreg3
344B        %vreg11<def> = S_ADD_I32 %vreg3:sub3, 68, %SCC<imp-def,dead>;
SReg_32:%vreg11 SReg_128:%vreg3
352B        %vreg21:sub2<def> = COPY %vreg14; VReg_128:%vreg21 SReg_32:%vreg14
368B        %vreg21:sub3<def> = COPY %vreg11; VReg_128:%vreg21 SReg_32:%vreg11
384B        BUFFER_STORE_DWORDX4_OFFSET %vreg21, %vreg8, 0, 0, 0, 0, 0,
%EXEC<imp-use>; mem:ST16[%out(addrspace=1)] VReg_128:%vreg21 SReg_128:%vreg8
400B        S_ENDPGM

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