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<base href="https://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW " title="NEW --- - Register allocation hints should understand sub registers" href="https://urldefense.proofpoint.com/v2/url?u=https-3A__llvm.org_bugs_show-5Fbug.cgi-3Fid-3D24192&d=AwMBaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=pF93YEPyB-J_PERP4DUZOJDzFVX5ZQ57vQk33wu0vio&m=lo6_yvv4W2ngfPYRxdHxnVsieIfJscvhJTlWZwv3x0M&s=oeMEcX_AabGqL2hCASICFlzPRiewim0CQLNJcMbnqqc&e=">24192</a>
</td>
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<th>Summary</th>
<td>Register allocation hints should understand sub registers
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Register Allocator
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>Matthew.Arsenault@amd.com
</td>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu, matze@braunis.de, qcolombet@apple.com
</td>
</tr>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>I'm trying to use MachineRegisterInfo::setRegAllocationHint to prefer that some
add instructions have the same source and dest register so that they can be
replaced with a += immediate add instruction. This mostly works, but doesn't
really work well for vectors.
define void @s_addk_v4i32_k0(<4 x i32> addrspace(1)* %out, <4 x i32> %b) {
%add = add <4 x i32> %b, <i32 65, i32 66, i32 67, i32 68>
store <4 x i32> %add, <4 x i32> addrspace(1)* %out
ret void
}
In this case, I want to hint that the destination and source registers are the
same. For the vector case, the destination register is a 4 component super
register. The source registers are 32-bit virtual registers. There isn't a way
to hint that the 32-bit vreg source register should be allocated to the
physical sub register of the destination.
Live Ins: %SGPR0_SGPR1
16B %vreg0<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg0
32B %vreg8:sub0_sub1<def,read-undef> = S_LOAD_DWORDX2_IMM %vreg0, 9;
mem:LD8[undef(addrspace=2)](nontemporal)(invariant) SReg_128:%vreg8
SReg_64:%vreg0
48B %vreg3<def> = S_LOAD_DWORDX4_IMM %vreg0, 13;
mem:LD16[undef(addrspace=2)](nontemporal)(invariant) SReg_128:%vreg3
SReg_64:%vreg0
96B %vreg8:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg8
112B %vreg8:sub2<def> = S_MOV_B32 -1; SReg_128:%vreg8
304B %vreg20<def> = S_ADD_I32 %vreg3:sub0, 65, %SCC<imp-def,dead>;
SReg_32:%vreg20 SReg_128:%vreg3
312B %vreg17<def> = S_ADD_I32 %vreg3:sub1, 66, %SCC<imp-def,dead>;
SReg_32:%vreg17 SReg_128:%vreg3
320B %vreg21:sub0<def,read-undef> = COPY %vreg20; VReg_128:%vreg21
SReg_32:%vreg20
336B %vreg21:sub1<def> = COPY %vreg17; VReg_128:%vreg21 SReg_32:%vreg17
340B %vreg14<def> = S_ADD_I32 %vreg3:sub2, 67, %SCC<imp-def,dead>;
SReg_32:%vreg14 SReg_128:%vreg3
344B %vreg11<def> = S_ADD_I32 %vreg3:sub3, 68, %SCC<imp-def,dead>;
SReg_32:%vreg11 SReg_128:%vreg3
352B %vreg21:sub2<def> = COPY %vreg14; VReg_128:%vreg21 SReg_32:%vreg14
368B %vreg21:sub3<def> = COPY %vreg11; VReg_128:%vreg21 SReg_32:%vreg11
384B BUFFER_STORE_DWORDX4_OFFSET %vreg21, %vreg8, 0, 0, 0, 0, 0,
%EXEC<imp-use>; mem:ST16[%out(addrspace=1)] VReg_128:%vreg21 SReg_128:%vreg8
400B S_ENDPGM</pre>
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