[llvm-branch-commits] [llvm] [AMDGPU] Set Format/FormatModifier directly instead of per-flag bits, NFC. (PR #223785)
Valery Pykhtin via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Sep 17 02:05:51 PDT 2026
https://github.com/vpykhtin updated https://github.com/llvm/llvm-project/pull/223785
>From 3d6cd385d58f00c03b4c98f54a150941696f4eeb Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at amd.com>
Date: Tue, 15 Sep 2026 16:55:47 +0000
Subject: [PATCH] [AMDGPU] Set Format/FormatModifier directly instead of
per-flag bits, NFC.
Remove the now-redundant individual InstSI format flag fields (SOP1/2/C/K/P,
VOP1/2/C/VOP3/VINTRP/VOPD3/LDSDIR, the memory formats, Spill, and DPP/SDWA) and
have instruction classes set the Format / FormatModifier enum fields directly.
The enum fields are packed into TSFlags exactly as before, so this is NFC (the
full instruction table is byte-identical).
Real instructions copy Format/FormatModifier from their pseudo in the base real
classes (kept next to the existing TSFlags copy), so the Format field is now
correct on real instructions too.
Two derived helper bits (IsVOP3Encoding, VOPD3) are computed from Format for the
getVOPe32/getVOPe64 relation maps and the VOPDPairs searchable table; they are
not part of TSFlags.
Co-Authored-By: Claude <noreply at anthropic.com>
---
llvm/lib/Target/AMDGPU/BUFInstructions.td | 14 +--
llvm/lib/Target/AMDGPU/DSDIRInstructions.td | 2 +-
llvm/lib/Target/AMDGPU/DSInstructions.td | 5 +-
llvm/lib/Target/AMDGPU/EXPInstructions.td | 2 +-
llvm/lib/Target/AMDGPU/FLATInstructions.td | 8 +-
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 10 +--
llvm/lib/Target/AMDGPU/SIInstrFormats.td | 90 ++++---------------
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 4 +-
llvm/lib/Target/AMDGPU/SIInstructions.td | 22 ++---
llvm/lib/Target/AMDGPU/SMInstructions.td | 6 +-
llvm/lib/Target/AMDGPU/SOPInstructions.td | 25 +++---
llvm/lib/Target/AMDGPU/VINTERPInstructions.td | 4 +-
llvm/lib/Target/AMDGPU/VOP1Instructions.td | 9 +-
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 5 +-
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 14 +--
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 17 ++--
llvm/lib/Target/AMDGPU/VOPDInstructions.td | 2 +-
llvm/lib/Target/AMDGPU/VOPInstructions.td | 38 ++++----
18 files changed, 121 insertions(+), 156 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 057c0f103ce80..0f2b429b2614b 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -114,7 +114,7 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins,
BUF_Pseudo <opName, outs, ins, asmOps, pattern> {
Instruction BaseOpcode = !cast<Instruction>(MTBUFGetBaseOpcode<NAME>.ret);
- let MTBUF = 1;
+ let Format = AMDGPUInstrFormat.MTBUF;
}
class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
@@ -125,7 +125,6 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let VM_CNT = 1;
let EXP_CNT = 1;
- let MTBUF = 1;
// copy relevant pseudo op flags
let UseNamedOperandTable = ps.UseNamedOperandTable;
@@ -133,6 +132,8 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
@@ -329,7 +330,7 @@ class MUBUF_Pseudo <string opName, dag outs, dag ins,
BUF_Pseudo <opName, outs, ins, asmOps, pattern> {
Instruction BaseOpcode = !cast<Instruction>(MUBUFGetBaseOpcode<NAME>.ret);
- let MUBUF = 1;
+ let Format = AMDGPUInstrFormat.MUBUF;
let AsmMatchConverter = "cvtMubuf";
let usesCustomInserter = 1;
}
@@ -342,13 +343,14 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let VM_CNT = 1;
let EXP_CNT = 1;
- let MUBUF = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -2640,6 +2642,8 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -2649,8 +2653,6 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let IsAtomicNoRet = ps.IsAtomicNoRet;
let VALU = ps.VALU;
let LGKM_CNT = ps.LGKM_CNT;
- let MUBUF = ps.MUBUF;
- let MTBUF = ps.MTBUF;
let Uses = ps.Uses;
let Defs = ps.Defs;
let isConvergent = ps.isConvergent;
diff --git a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
index 09053b324e063..ba9152053d20f 100644
--- a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
@@ -67,7 +67,7 @@ class VDSDIR_getIns<bit direct> {
class DSDIR_Common<string opName, string asm = "", dag ins, bit direct> :
InstSI<(outs VGPR_32:$vdst), ins, asm> {
- let LDSDIR = 1;
+ let Format = AMDGPUInstrFormat.LDSDIR;
let EXP_CNT = 1;
let hasSideEffects = 0;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 62dba320306f5..ee3578c180335 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -11,7 +11,7 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
SIMCInstr <NAME, SIEncodingFamily.NONE> {
let LGKM_CNT = 1;
- let DS = 1;
+ let Format = AMDGPUInstrFormat.DS;
let GWS = 0;
let Size = 8;
let UseNamedOperandTable = 1;
@@ -58,7 +58,6 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let isPseudo = 0;
let isCodeGenOnly = 0;
let LGKM_CNT = 1;
- let DS = 1;
let UseNamedOperandTable = 1;
// copy relevant pseudo op flags
@@ -66,6 +65,8 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let SubtargetPredicate = ps.SubtargetPredicate;
let WaveSizePredicate = ps.WaveSizePredicate;
let OtherPredicates = ps.OtherPredicates;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td
index c9b236ab1f06a..4778b54cf63ba 100644
--- a/llvm/lib/Target/AMDGPU/EXPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td
@@ -16,7 +16,7 @@ class EXPCommon<bit _row, bit _done, string asm = ""> : InstSI<
ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
exp_vm:$vm, exp_compr:$compr, i32imm:$en),
asm> {
- let EXP = 1;
+ let Format = AMDGPUInstrFormat.EXP;
let EXP_CNT = 1;
let mayLoad = _done;
let mayStore = 1;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index f241f6677d22b..0281d2cdc34ce 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -39,7 +39,7 @@ class FLAT_Pseudo<string opName, dag outs, dag ins,
let isPseudo = 1;
let isCodeGenOnly = 1;
- let FLAT = 1;
+ let Format = AMDGPUInstrFormat.FLAT;
let UseNamedOperandTable = 1;
let hasSideEffects = 0;
@@ -99,12 +99,13 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
let isPseudo = 0;
let isCodeGenOnly = 0;
- let FLAT = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -175,13 +176,14 @@ class VFLAT_Real <bits<8> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands, []>,
Enc96 {
- let FLAT = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let WaveSizePredicate = ps.WaveSizePredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 1a53d2a1898e5..9ae7c6dad18f0 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -203,7 +203,7 @@ class MIMG_Base <dag outs, string dns = "">
let VM_CNT = 1;
let EXP_CNT = 1;
- let MIMG = 1;
+ let Format = AMDGPUInstrFormat.MIMG;
let Uses = [EXEC];
let mayLoad = 1;
let mayStore = 0;
@@ -379,8 +379,7 @@ class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
class VIMAGE<int op, dag outs, int num_addrs, Predicate pred,
MIMGEncoding encoding, string dns="", list<RegisterOperand> addr_types=[]>
: MIMG<outs, dns>, VIMAGEe<op> {
- let MIMG = 0;
- let VIMAGE = 1;
+ let Format = AMDGPUInstrFormat.VIMAGE;
let SubtargetPredicate = pred;
let AssemblerPredicate = pred;
@@ -403,8 +402,7 @@ class VIMAGE<int op, dag outs, int num_addrs, Predicate pred,
class VSAMPLE<int op, dag outs, int num_addrs, Predicate pred,
MIMGEncoding encoding, string dns="", RegisterOperand Addr3RC>
: MIMG<outs, dns>, VSAMPLEe<op> {
- let MIMG = 0;
- let VSAMPLE = 1;
+ let Format = AMDGPUInstrFormat.VSAMPLE;
let SubtargetPredicate = pred;
let AssemblerPredicate = pred;
@@ -2224,6 +2222,8 @@ class VIMAGE_TENSOR_Real <bits<8> op, VIMAGE_TENSOR_Pseudo ps, string opName = p
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index a0c25cc99c018..b05294e2707ef 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -62,45 +62,22 @@ class InstSI <dag outs, dag ins, string asm = "",
field bit SALU = 0;
field bit VALU = 0;
- // SALU instruction formats.
- field bit SOP1 = 0;
- field bit SOP2 = 0;
- field bit SOPC = 0;
- field bit SOPK = 0;
- field bit SOPP = 0;
-
- // VALU instruction formats.
- field bit VOP1 = 0;
- field bit VOP2 = 0;
- field bit VOPC = 0;
- field bit VOP3 = 0;
- field bit VOP3P = 0;
- field bit VINTRP = 0;
- field bit SDWA = 0;
- field bit DPP = 0;
- field bit TRANS = 0;
+ // Mutually-exclusive instruction format, set directly by instruction classes.
+ field bits<5> Format = AMDGPUInstrFormat.NONE;
- // Memory instruction formats.
- field bit MUBUF = 0;
- field bit MTBUF = 0;
- field bit SMRD = 0;
- field bit MIMG = 0;
- field bit VIMAGE = 0;
- field bit VSAMPLE = 0;
- field bit EXP = 0;
- field bit FLAT = 0;
- field bit DS = 0;
-
- // Combined SGPR/VGPR spill bit
- field bit Spill = 0;
+ // Mutually-exclusive operand-encoding modifier (DPP/SDWA).
+ field bits<2> FormatModifier = AMDGPUFormatModifier.None;
- // LDSDIR instruction format.
- field bit LDSDIR = 0;
+ // Derived from Format (not part of TSFlags); only used as an instruction-
+ // relation-map key to tell the VOP3/e64 encoding apart from e32/sdwa/dpp.
+ bit IsVOP3Encoding = !eq(Format, AMDGPUInstrFormat.VOP3);
- // VINTERP instruction format.
- field bit VINTERP = 0;
+ // Derived from Format (not part of TSFlags); only used as a searchable-table
+ // key (VOPDPairs) to tell VOPD3 apart from the plain VOPD encoding.
+ bit VOPD3 = !eq(Format, AMDGPUInstrFormat.VOPD3);
- field bit VOPD3 = 0;
+ // Transcendental property flag (orthogonal to the format).
+ field bit TRANS = 0;
// High bits - other information.
field bit VM_CNT = 0;
@@ -201,40 +178,6 @@ class InstSI <dag outs, dag ins, string asm = "",
// This bit indicates that this is one of SWMMAC instructions.
field bit IsSWMMAC = 0;
- // Mutually-exclusive instruction format, derived from the format bits above.
- // The base format bits are all exclusive, so they collapse into one enum
- // field. VOP3P/VINTERP also set the VOP3 bit, so match them before VOP3.
- bits<5> Format = !cond(SOP1 : AMDGPUInstrFormat.SOP1,
- SOP2 : AMDGPUInstrFormat.SOP2,
- SOPC : AMDGPUInstrFormat.SOPC,
- SOPK : AMDGPUInstrFormat.SOPK,
- SOPP : AMDGPUInstrFormat.SOPP,
- VOP1 : AMDGPUInstrFormat.VOP1,
- VOP2 : AMDGPUInstrFormat.VOP2,
- VOPC : AMDGPUInstrFormat.VOPC,
- VOP3P : AMDGPUInstrFormat.VOP3P,
- VINTERP : AMDGPUInstrFormat.VINTERP,
- VOP3 : AMDGPUInstrFormat.VOP3,
- VINTRP : AMDGPUInstrFormat.VINTRP,
- VOPD3 : AMDGPUInstrFormat.VOPD3,
- LDSDIR : AMDGPUInstrFormat.LDSDIR,
- MUBUF : AMDGPUInstrFormat.MUBUF,
- MTBUF : AMDGPUInstrFormat.MTBUF,
- SMRD : AMDGPUInstrFormat.SMRD,
- MIMG : AMDGPUInstrFormat.MIMG,
- VIMAGE : AMDGPUInstrFormat.VIMAGE,
- VSAMPLE : AMDGPUInstrFormat.VSAMPLE,
- EXP : AMDGPUInstrFormat.EXP,
- FLAT : AMDGPUInstrFormat.FLAT,
- DS : AMDGPUInstrFormat.DS,
- Spill : AMDGPUInstrFormat.Spill,
- true : AMDGPUInstrFormat.NONE);
-
- // Mutually-exclusive operand-encoding modifier (DPP and SDWA never co-occur).
- bits<2> FormatModifier = !cond(DPP : AMDGPUFormatModifier.DPP,
- SDWA : AMDGPUFormatModifier.SDWA,
- true : AMDGPUFormatModifier.None);
-
let TSFlags{4-0} = Format;
let TSFlags{6-5} = FormatModifier;
@@ -303,7 +246,12 @@ class InstSI <dag outs, dag ins, string asm = "",
let AsmVariantName = AMDGPUAsmVariants.Default;
// Avoid changing source registers in a way that violates constant bus read limitations.
- let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
+ let hasExtraSrcRegAllocReq = !or(!eq(Format, AMDGPUInstrFormat.VOP1),
+ !eq(Format, AMDGPUInstrFormat.VOP2),
+ !eq(Format, AMDGPUInstrFormat.VOPC),
+ !eq(Format, AMDGPUInstrFormat.VOP3),
+ !eq(FormatModifier, AMDGPUFormatModifier.SDWA),
+ VALU);
}
class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
@@ -587,7 +535,7 @@ let Uses = [EXEC] in {
class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
- let VINTRP = 1;
+ let Format = AMDGPUInstrFormat.VINTRP;
// VINTRP instructions read parameter values from LDS, but these parameter
// values are stored outside of the LDS memory that is allocated to the
// shader for general purpose use.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 1df90ebbe9216..b44d2782e0d33 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3377,7 +3377,7 @@ multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
def getVOPe64 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
- let ColFields = ["Size", "VOP3"];
+ let ColFields = ["Size", "IsVOP3Encoding"];
let KeyCol = ["4", "0"];
let ValueCols = [["8", "1"]];
}
@@ -3386,7 +3386,7 @@ def getVOPe64 : InstrMapping {
def getVOPe32 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
- let ColFields = ["Size", "VOP3"];
+ let ColFields = ["Size", "IsVOP3Encoding"];
let KeyCol = ["8", "1"];
let ValueCols = [["4", "0"]];
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e891ba31bbf67..fe780ffb84f16 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -138,7 +138,7 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
let isMoveImm = 1;
let SchedRW = [Write64Bit];
let Size = 4;
- let VOP1 = 1; // Not entirely correct, but close enough.
+ let Format = AMDGPUInstrFormat.VOP1; // Not entirely correct, but close enough.
let UseNamedOperandTable = 1;
}
@@ -154,7 +154,7 @@ def AV_MOV_B32_IMM_PSEUDO
// Imprecise, technically if AGPR it's VOP3 and VOP1 for VGPR. But
// this tricks the rematerialize logic into working for it.
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let isMoveImm = 1;
let SchedRW = [Write32Bit];
let Size = 8;
@@ -173,7 +173,7 @@ def AV_MOV_B64_IMM_PSEUDO
// Imprecise, technically if AGPR it's 2 x VOP3 and 2 x VOP1 for
// VGPR. But this tricks the rematerialize logic into working for
// it.
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let isMoveImm = 1;
let SchedRW = [Write32Bit, Write32Bit];
let Size = 16; // 2 x v_accwrite_write_b32 in the worst case
@@ -517,7 +517,7 @@ class WrapTerminatorVOPC<VOPC_Pseudo base_inst> : VPseudoInstSI<
let isTerminator = 1;
let isConvergent = 1;
let isCompare = 1;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
}
let SubtargetPredicate = HasNoSdstCMPX in {
@@ -1076,7 +1076,7 @@ class INDIRECT_REG_WRITE_MOVREL_pseudo<RegisterClass rc,
class V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<RegisterClass rc> :
INDIRECT_REG_WRITE_MOVREL_pseudo<rc, VSrc_b32> {
let VALU = 1;
- let VOP1 = 1;
+ let Format = AMDGPUInstrFormat.VOP1;
let Uses = [M0, EXEC];
}
@@ -1084,7 +1084,7 @@ class S_INDIRECT_REG_WRITE_MOVREL_pseudo<RegisterClass rc,
RegisterOperand val_ty> :
INDIRECT_REG_WRITE_MOVREL_pseudo<rc, val_ty> {
let SALU = 1;
- let SOP1 = 1;
+ let Format = AMDGPUInstrFormat.SOP1;
let Uses = [M0];
}
@@ -1180,7 +1180,7 @@ def V_INDIRECT_REG_READ_GPR_IDX_B32_V16 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VRe
def V_INDIRECT_REG_READ_GPR_IDX_B32_V32 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_1024>;
multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
- let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
+ let UseNamedOperandTable = 1, Format = AMDGPUInstrFormat.Spill, SALU = 1, Uses = [EXEC] in {
def _SAVE : PseudoInstSI <
(outs),
(ins sgpr_class:$data, i32imm:$addr)> {
@@ -1221,7 +1221,7 @@ defm SI_SPILL_S384 : SI_SPILL_SGPR <SReg_384>;
defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
defm SI_SPILL_S1024 : SI_SPILL_SGPR <SReg_1024>;
-let Spill = 1, VALU = 1, isConvergent = 1 in {
+let Format = AMDGPUInstrFormat.Spill, VALU = 1, isConvergent = 1 in {
def SI_SPILL_S32_TO_VGPR : PseudoInstSI <(outs VGPR_32:$vdst),
(ins SReg_32:$src0, i32imm:$src1, VGPR_32:$vdst_in)> {
let Size = 4;
@@ -1243,14 +1243,14 @@ def SI_RESTORE_S32_FROM_VGPR : PseudoInstSI <(outs SReg_32:$sdst),
let mayStore = 0;
let hasExtraSrcRegAllocReq = 1;
}
-} // End Spill = 1, VALU = 1, isConvergent = 1
+} // End Format = AMDGPUInstrFormat.Spill, VALU = 1, isConvergent = 1
// VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
// needs to be used and an extra instruction to move between VGPR and AGPR.
// UsesTmp adds to the total size of an expanded spill in this case.
multiclass SI_SPILL_VGPR <SIRegisterClassLike vgpr_class,
bit UsesTmp = 0, bit HasMask = 0> {
- let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
+ let UseNamedOperandTable = 1, Format = AMDGPUInstrFormat.Spill, VALU = 1,
SchedRW = [WriteVMEM] in {
def _SAVE : VPseudoInstSI <
(outs),
@@ -1293,7 +1293,7 @@ multiclass SI_SPILL_VGPR <SIRegisterClassLike vgpr_class,
// Size field is unsigned char and cannot fit more.
let Size = !if(!le(MaxSize, 256), MaxSize, 252);
}
- } // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
+ } // End UseNamedOperandTable = 1, Format = AMDGPUInstrFormat.Spill, VALU = 1, SchedRW = [WriteVMEM]
}
// TODO: Technically the AlignTarget register class constraint is
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 19aeafe9b30cc..ec4422d2d484b 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -33,7 +33,7 @@ class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
let isCodeGenOnly = 1;
let LGKM_CNT = 1;
- let SMRD = 1;
+ let Format = AMDGPUInstrFormat.SMRD;
let mayStore = 0;
let mayLoad = 1;
let hasSideEffects = 0;
@@ -63,7 +63,6 @@ class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
// copy relevant pseudo op flags
let LGKM_CNT = ps.LGKM_CNT;
- let SMRD = ps.SMRD;
let mayStore = ps.mayStore;
let mayLoad = ps.mayLoad;
let hasSideEffects = ps.hasSideEffects;
@@ -77,7 +76,8 @@ class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
let Uses = ps.Uses;
let Defs = ps.Defs;
let isConvergent = ps.isConvergent;
-
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
bit is_buffer = ps.is_buffer;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index bdcef208f52e9..fcd3184bf612c 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -35,7 +35,7 @@ class SOP1_Pseudo <string opName, dag outs, dag ins,
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
- let SOP1 = 1;
+ let Format = AMDGPUInstrFormat.SOP1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
@@ -49,12 +49,13 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
Enc32 {
let SALU = 1;
- let SOP1 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
let Size = 4;
// copy relevant pseudo op flags
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let SchedRW = ps.SchedRW;
@@ -585,7 +586,7 @@ class SOP2_Pseudo<string opName, dag outs, dag ins,
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
- let SOP2 = 1;
+ let Format = AMDGPUInstrFormat.SOP2;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
@@ -602,7 +603,6 @@ class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList,
name # ps.AsmOperands> {
let SALU = 1;
- let SOP2 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -610,6 +610,8 @@ class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
@@ -1018,7 +1020,7 @@ class SOPK_Pseudo <string opName, dag outs, dag ins,
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
- let SOPK = 1;
+ let Format = AMDGPUInstrFormat.SOPK;
let FixedSize = 1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
@@ -1030,12 +1032,13 @@ class SOPK_Real<SOPK_Pseudo ps, string name = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList,
name # ps.AsmOperands> {
let SALU = 1;
- let SOPK = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
let UseNamedOperandTable = 1;
// copy relevant pseudo op flags
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints;
@@ -1296,7 +1299,7 @@ class SOPC_Pseudo<string opName, dag outs, dag ins,
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
- let SOPC = 1;
+ let Format = AMDGPUInstrFormat.SOPC;
let Defs = [SCC];
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
@@ -1307,7 +1310,6 @@ class SOPC_Real<bits<7> op, SOPC_Pseudo ps> :
ps.Mnemonic # ps.AsmOperands>,
Enc32 {
let SALU = 1;
- let SOPC = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -1316,6 +1318,8 @@ class SOPC_Real<bits<7> op, SOPC_Pseudo ps> :
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
@@ -1482,7 +1486,7 @@ class SOPP_Pseudo<string opName, dag ins,
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
- let SOPP = 1;
+ let Format = AMDGPUInstrFormat.SOPP;
let FixedSize = 1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
@@ -1500,7 +1504,6 @@ class SOPP_Real<SOPP_Pseudo ps, string name = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList,
name # ps.AsmOperands> {
let SALU = 1;
- let SOPP = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -1509,6 +1512,8 @@ class SOPP_Real<SOPP_Pseudo ps, string name = ps.Mnemonic> :
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
diff --git a/llvm/lib/Target/AMDGPU/VINTERPInstructions.td b/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
index 2030cf1ee76a7..b2b51f16499e9 100644
--- a/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
@@ -58,12 +58,12 @@ class VINTERP_Pseudo <string OpName, VOPProfile P, list<dag> pattern = []> :
let mayRaiseFPException = 0;
let VOP3_OPSEL = 1;
- let VINTERP = 1;
+ let Format = AMDGPUInstrFormat.VINTERP;
}
class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily, string asmName> :
VOP3_Real <ps, EncodingFamily, asmName> {
- let VINTERP = 1;
+ let Format = AMDGPUInstrFormat.VINTERP;
let IsSingle = 1;
}
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index b9dab2e19bdc9..f025c18fa07a6 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -53,7 +53,7 @@ class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1On
let mayRaiseFPException = ReadsModeReg;
- let VOP1 = 1;
+ let Format = AMDGPUInstrFormat.VOP1;
let VALU = 1;
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
@@ -66,7 +66,6 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let VALU = 1;
- let VOP1 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -79,6 +78,8 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let AsmMatchConverter = ps.AsmMatchConverter;
let AsmVariantName = ps.AsmVariantName;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
@@ -1729,7 +1730,7 @@ defm V_CVT_NORM_U16_F16 : VOP1_Real_vi<0x4e>;
defm V_ACCVGPR_MOV_B32 : VOP1Only_Real_vi<0x52>;
-let VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [EXEC, M0], Size = V_MOV_B32_e32.Size in {
+let Format = AMDGPUInstrFormat.VOP1, SubtargetPredicate = isGFX8GFX9, Uses = [EXEC, M0], Size = V_MOV_B32_e32.Size in {
// Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
// indexing mode. vdst can't be treated as a def for codegen purposes,
@@ -1747,7 +1748,7 @@ def V_MOV_B32_indirect_read : VPseudoInstSI<
PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
getVOPSrc0ForVT<i32, 0>.ret:$src0)>;
-} // End VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [M0]
+} // End Format = AMDGPUInstrFormat.VOP1, SubtargetPredicate = isGFX8GFX9, Uses = [M0]
let OtherPredicates = [isGFX8Plus] in {
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index bcf2ca6e8729e..c3f047957c172 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -87,7 +87,7 @@ class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suf
let mayRaiseFPException = ReadsModeReg;
- let VOP2 = 1;
+ let Format = AMDGPUInstrFormat.VOP2;
let VALU = 1;
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
@@ -100,7 +100,6 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let VALU = 1;
- let VOP2 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -113,6 +112,8 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let AsmMatchConverter = ps.AsmMatchConverter;
let AsmVariantName = ps.AsmVariantName;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 47321d561de73..16b1123f5ac54 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -80,7 +80,7 @@ multiclass VOP3PInst<string OpName, VOPProfile P,
let SubtargetPredicate = isGFX11Plus in {
if P.HasExtVOP3DPP then
def _dpp : VOP3_DPP_Pseudo<OpName, P> {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let PseudoInstr = OpName #"_dpp";
}
} // end SubtargetPredicate = isGFX11Plus
@@ -97,7 +97,7 @@ multiclass VOP3PInstDotWithDual<string OpName, VOPProfile P,
let SubtargetPredicate = isGFX11Plus in {
if P.HasExtVOP3DPP then
def _dpp : VOP3_DPP_Pseudo<OpName, P> {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let PseudoInstr = OpName #"_dpp";
}
} // end SubtargetPredicate = isGFX11Plus
@@ -112,7 +112,7 @@ multiclass VOP3_VOP3PInst<string OpName, VOP3P_Mix_Profile P> {
let SubtargetPredicate = isGFX11Plus in {
if P.HasExtVOP3DPP then
def _dpp : VOP3_DPP_Pseudo<OpName, P> {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let PseudoInstr = OpName#"_dpp";
let Constraints = !if(P.UseTiedOutput, "$vdst = $vdst_in", "");
}
@@ -124,7 +124,7 @@ multiclass VOP3_VOP3PInst_t16<string OpName, VOP3P_Mix_Profile P> {
if P.HasExtVOP3DPP then
def _dpp : VOP3_DPP_Pseudo<OpName, P> {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let PseudoInstr = OpName#"_dpp";
}
}
@@ -2922,7 +2922,7 @@ multiclass VOP3P_Real_vi<bits<7> op> {
VOP3Pe_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
let AssemblerPredicate = HasVOP3PInsts;
let DecoderNamespace = "GFX8";
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
}
}
@@ -3258,12 +3258,12 @@ defm V_PK_MOV_B32 : VOP3P_Real_vi <0x33>;
// GFX10, GFX11, GFX12, GFX13.
//===----------------------------------------------------------------------===//
-let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
+let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", Format = AMDGPUInstrFormat.VOP3P in {
multiclass VOP3P_Real_gfx10<bits<8> op> {
def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
VOP3Pe_gfx10 <op, !cast<VOP3P_Pseudo>(NAME).Pfl>;
}
-} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1
+} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", Format = AMDGPUInstrFormat.VOP3P
multiclass VOP3P_Real_gfx10_gfx11<bits<8> op> :
VOP3P_Real_gfx10<op>, VOP3P_Real_Base<GFX11Gen, op>;
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index aae00bdcb03f2..cb5bd5f63c6f7 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -234,7 +234,7 @@ class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
let ReadsModeReg = P.Src0VT.isFP;
let VALU = 1;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
let Defs = !if(DefVcc, [VCC], []);
@@ -246,7 +246,6 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.Pseudo
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let VALU = 1;
- let VOPC = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -258,6 +257,8 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.Pseudo
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
@@ -408,7 +409,7 @@ multiclass VOPC_Pseudos <string opName,
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
let SchedRW = P.Schedule;
let isCompare = 1;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
let Constraints = "";
}
if P.HasExtVOP3DPP then
@@ -472,7 +473,7 @@ multiclass VOPCX_Pseudos <string opName,
let Defs = [EXEC];
let SchedRW = P_NoSDst.Schedule;
let isCompare = 1;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
let Constraints = "";
}
if P.HasExtVOP3DPP then
@@ -1105,7 +1106,7 @@ multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
!if(DefVcc, [VCC], []));
let SchedRW = p.Schedule;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
let Constraints = "";
}
if p.HasExtVOP3DPP then
@@ -1154,7 +1155,7 @@ multiclass VOPCX_Class_Pseudos <string opName,
def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
let Defs = [EXEC];
let SchedRW = P_NoSDst.Schedule;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
let Constraints = "";
}
if P.HasExtVOP3DPP then
@@ -1467,7 +1468,7 @@ class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
let Inst{63-60} = row_mask;
let AsmMatchConverter = "cvtDPP";
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
}
class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
@@ -1485,7 +1486,7 @@ class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
let Inst{63-40} = dpp8{23-0};
let AsmMatchConverter = "cvtDPP8";
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
}
class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
diff --git a/llvm/lib/Target/AMDGPU/VOPDInstructions.td b/llvm/lib/Target/AMDGPU/VOPDInstructions.td
index 1fadb8999b14b..e01a7535f0885 100644
--- a/llvm/lib/Target/AMDGPU/VOPDInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPDInstructions.td
@@ -167,7 +167,7 @@ class VOPD3<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
: VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,
VOPD3e<XasVC.VOPDOp, YasVC.VOPDOp, VDX, VDY> {
- let VOPD3 = 1;
+ let Format = AMDGPUInstrFormat.VOPD3;
let Size = 12;
// VOPD3 uses promoted form of VOP2 instructions, so V_CNDMASK_B32 is not
// limited to VCC src2 only, and a real SGPR will be used as an operand
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index be47521637113..32368155d0c9b 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -87,7 +87,7 @@ class VOP3Common <dag outs, dag ins, string asm = "",
// zero (or less than zero).
let AddedComplexity = -1000;
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let AsmVariantName = AMDGPUAsmVariants.VOP3;
let AsmMatchConverter = !if(HasMods, "cvtVOP3", "");
@@ -137,7 +137,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
// zero (or less than zero).
let AddedComplexity = -1000;
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let VALU = 1;
let FPClamp = P.HasFPClamp;
let IntClamp = P.HasIntClamp;
@@ -160,7 +160,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
VOP3_Pseudo<opName, P, pattern, 1> {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let IsDOT = P.IsDOT;
}
@@ -176,7 +176,6 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemoni
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let VALU = 1;
- let VOP3 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
let UseNamedOperandTable = 1;
@@ -189,6 +188,8 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemoni
let AsmMatchConverter = ps.AsmMatchConverter;
let AsmVariantName = ps.AsmVariantName;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
@@ -780,7 +781,7 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
let hasSideEffects = 0;
let VALU = 1;
- let SDWA = 1;
+ let FormatModifier = AMDGPUFormatModifier.SDWA;
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
@@ -798,7 +799,6 @@ class VOP_SDWA8_Real <VOP_SDWA_Pseudo ps> :
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
let VALU = 1;
- let SDWA = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -816,6 +816,8 @@ class VOP_SDWA8_Real <VOP_SDWA_Pseudo ps> :
let UseNamedOperandTable = ps.UseNamedOperandTable;
let DecoderNamespace = ps.DecoderNamespace;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let Uses = ps.Uses;
let Defs = ps.Defs;
@@ -830,7 +832,6 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> {
let VALU = 1;
- let SDWA = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -851,6 +852,8 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let Uses = ps.Uses;
let Defs = ps.Defs;
@@ -1016,7 +1019,7 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[],
let hasSideEffects = 0;
let VALU = 1;
- let DPP = 1;
+ let FormatModifier = AMDGPUFormatModifier.DPP;
let Size = 8;
let IsPacked = P.IsPacked;
@@ -1041,7 +1044,7 @@ class VOP3_DPP_Pseudo <string OpName, VOPProfile P> :
let PseudoInstr = OpName#"_e64"#"_dpp";
let OutOperandList = P.OutsVOP3DPP;
let Size = 12;
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let AsmMatchConverter = "cvtVOP3DPP";
let AsmVariantName = !if(!or(P.HasExtVOP3DPP, P.HasExt64BitDPP),
AMDGPUAsmVariants.VOP3_DPP,
@@ -1053,7 +1056,6 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
let VALU = 1;
- let DPP = 1;
let isConvergent = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -1074,6 +1076,8 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
let UseNamedOperandTable = ps.UseNamedOperandTable;
let DecoderNamespace = ps.DecoderNamespace;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let Uses = ps.Uses;
let Defs = ps.Defs;
@@ -1094,7 +1098,7 @@ class VOP_DPP_Base <string OpName, VOPProfile P,
let UseNamedOperandTable = 1;
let VALU = 1;
- let DPP = 1;
+ let FormatModifier = AMDGPUFormatModifier.DPP;
let isConvergent = 1;
let Size = 8;
@@ -1117,7 +1121,7 @@ class VOP3_DPP_Base <string OpName, VOPProfile P, bit IsDPP16,
VOP_DPP_Base<OpName, P, InsDPP, AsmDPP> {
let OutOperandList = P.OutsVOP3DPP;
let AsmMatchConverter = "cvtVOP3DPP";
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let AsmVariantName = !if(!or(P.HasExtVOP3DPP, P.HasExt64BitDPP),
AMDGPUAsmVariants.VOP3_DPP,
AMDGPUAsmVariants.Disable);
@@ -1172,7 +1176,7 @@ class VOP3P_DPP <bits<8> op, string OpName, VOPProfile P, bit IsDPP16,
VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3P_DPPe_Common<op, P>,
VOP3_DPPe_Fields {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let Inst{40-32} = 0xfa;
let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
@@ -1215,7 +1219,7 @@ class VOP_DPP8_Base<string OpName, VOPProfile P, dag InsDPP8 = P.InsDPP8, string
let UseNamedOperandTable = 1;
let VALU = 1;
- let DPP = 1;
+ let FormatModifier = AMDGPUFormatModifier.DPP;
let isConvergent = 1;
let Size = 8;
@@ -1236,7 +1240,7 @@ class VOP_DPP8_Pseudo<string OpName, VOPProfile P, list<dag> pattern=[]> :
let hasSideEffects = 0;
let VALU = 1;
- let DPP = 1;
+ let FormatModifier = AMDGPUFormatModifier.DPP;
let Size = 8;
let IsPacked = P.IsPacked;
@@ -1259,7 +1263,7 @@ class VOP3_DPP8_Base<string OpName, VOPProfile P> :
let AsmMatchConverter = "cvtVOP3DPP8";
let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP,
AMDGPUAsmVariants.Disable);
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let Size = 12;
}
@@ -1289,7 +1293,7 @@ class VOP3P_DPP8<bits<8> op, string OpName, VOPProfile P> :
VOP3_DPP8_Base<OpName, P>, VOP3P_DPPe_Common<op, P>,
VOP3_DPP8e_Fields {
- let VOP3P = 1;
+ let Format = AMDGPUInstrFormat.VOP3P;
let Inst{40-32} = fi;
let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{95-72} = dpp8{23-0};
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