[llvm-branch-commits] [llvm] [AMDGPU] Set Format/FormatModifier directly instead of per-flag bits, NFC. (PR #223785)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 15 11:55:33 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Valery Pykhtin (vpykhtin)
<details>
<summary>Changes</summary>
Remove the now-redundant individual InstSI format flag fields (SOP1/2/C/K/P,
VOP1/2/C/VOP3/VINTRP/VOPD3/LDSDIR, the memory formats, Spill, and DPP/SDWA) and
have instruction classes set the Format / FormatModifier enum fields directly.
The enum fields are packed into TSFlags exactly as before, so this is NFC (the
full instruction table is byte-identical).
Real instructions copy Format/FormatModifier from their pseudo in the base real
classes (kept next to the existing TSFlags copy), so the Format field is now
correct on real instructions too.
Two derived helper bits (IsVOP3Encoding, VOPD3) are computed from Format for the
getVOPe32/getVOPe64 relation maps and the VOPDPairs searchable table; they are
not part of TSFlags.
Co-Authored-By: Claude <noreply@<!-- -->anthropic.com>
---
Patch is 42.02 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223785.diff
18 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+8-6)
- (modified) llvm/lib/Target/AMDGPU/DSDIRInstructions.td (+1-1)
- (modified) llvm/lib/Target/AMDGPU/DSInstructions.td (+3-2)
- (modified) llvm/lib/Target/AMDGPU/EXPInstructions.td (+1-1)
- (modified) llvm/lib/Target/AMDGPU/FLATInstructions.td (+5-3)
- (modified) llvm/lib/Target/AMDGPU/MIMGInstructions.td (+5-5)
- (modified) llvm/lib/Target/AMDGPU/SIInstrFormats.td (+19-71)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+11-11)
- (modified) llvm/lib/Target/AMDGPU/SMInstructions.td (+3-3)
- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+15-10)
- (modified) llvm/lib/Target/AMDGPU/VINTERPInstructions.td (+2-2)
- (modified) llvm/lib/Target/AMDGPU/VOP1Instructions.td (+5-4)
- (modified) llvm/lib/Target/AMDGPU/VOP2Instructions.td (+3-2)
- (modified) llvm/lib/Target/AMDGPU/VOP3PInstructions.td (+7-7)
- (modified) llvm/lib/Target/AMDGPU/VOPCInstructions.td (+9-8)
- (modified) llvm/lib/Target/AMDGPU/VOPDInstructions.td (+1-1)
- (modified) llvm/lib/Target/AMDGPU/VOPInstructions.td (+21-17)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 057c0f103ce80..0f2b429b2614b 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -114,7 +114,7 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins,
BUF_Pseudo <opName, outs, ins, asmOps, pattern> {
Instruction BaseOpcode = !cast<Instruction>(MTBUFGetBaseOpcode<NAME>.ret);
- let MTBUF = 1;
+ let Format = AMDGPUInstrFormat.MTBUF;
}
class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
@@ -125,7 +125,6 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let VM_CNT = 1;
let EXP_CNT = 1;
- let MTBUF = 1;
// copy relevant pseudo op flags
let UseNamedOperandTable = ps.UseNamedOperandTable;
@@ -133,6 +132,8 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
@@ -329,7 +330,7 @@ class MUBUF_Pseudo <string opName, dag outs, dag ins,
BUF_Pseudo <opName, outs, ins, asmOps, pattern> {
Instruction BaseOpcode = !cast<Instruction>(MUBUFGetBaseOpcode<NAME>.ret);
- let MUBUF = 1;
+ let Format = AMDGPUInstrFormat.MUBUF;
let AsmMatchConverter = "cvtMubuf";
let usesCustomInserter = 1;
}
@@ -342,13 +343,14 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let VM_CNT = 1;
let EXP_CNT = 1;
- let MUBUF = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -2640,6 +2642,8 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let Constraints = ps.Constraints;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -2649,8 +2653,6 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let IsAtomicNoRet = ps.IsAtomicNoRet;
let VALU = ps.VALU;
let LGKM_CNT = ps.LGKM_CNT;
- let MUBUF = ps.MUBUF;
- let MTBUF = ps.MTBUF;
let Uses = ps.Uses;
let Defs = ps.Defs;
let isConvergent = ps.isConvergent;
diff --git a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
index 09053b324e063..ba9152053d20f 100644
--- a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td
@@ -67,7 +67,7 @@ class VDSDIR_getIns<bit direct> {
class DSDIR_Common<string opName, string asm = "", dag ins, bit direct> :
InstSI<(outs VGPR_32:$vdst), ins, asm> {
- let LDSDIR = 1;
+ let Format = AMDGPUInstrFormat.LDSDIR;
let EXP_CNT = 1;
let hasSideEffects = 0;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 62dba320306f5..ee3578c180335 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -11,7 +11,7 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
SIMCInstr <NAME, SIEncodingFamily.NONE> {
let LGKM_CNT = 1;
- let DS = 1;
+ let Format = AMDGPUInstrFormat.DS;
let GWS = 0;
let Size = 8;
let UseNamedOperandTable = 1;
@@ -58,7 +58,6 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let isPseudo = 0;
let isCodeGenOnly = 0;
let LGKM_CNT = 1;
- let DS = 1;
let UseNamedOperandTable = 1;
// copy relevant pseudo op flags
@@ -66,6 +65,8 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let SubtargetPredicate = ps.SubtargetPredicate;
let WaveSizePredicate = ps.WaveSizePredicate;
let OtherPredicates = ps.OtherPredicates;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td
index c9b236ab1f06a..4778b54cf63ba 100644
--- a/llvm/lib/Target/AMDGPU/EXPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td
@@ -16,7 +16,7 @@ class EXPCommon<bit _row, bit _done, string asm = ""> : InstSI<
ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
exp_vm:$vm, exp_compr:$compr, i32imm:$en),
asm> {
- let EXP = 1;
+ let Format = AMDGPUInstrFormat.EXP;
let EXP_CNT = 1;
let mayLoad = _done;
let mayStore = 1;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index f241f6677d22b..0281d2cdc34ce 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -39,7 +39,7 @@ class FLAT_Pseudo<string opName, dag outs, dag ins,
let isPseudo = 1;
let isCodeGenOnly = 1;
- let FLAT = 1;
+ let Format = AMDGPUInstrFormat.FLAT;
let UseNamedOperandTable = 1;
let hasSideEffects = 0;
@@ -99,12 +99,13 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
let isPseudo = 0;
let isCodeGenOnly = 0;
- let FLAT = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -175,13 +176,14 @@ class VFLAT_Real <bits<8> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands, []>,
Enc96 {
- let FLAT = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let WaveSizePredicate = ps.WaveSizePredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 1a53d2a1898e5..9ae7c6dad18f0 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -203,7 +203,7 @@ class MIMG_Base <dag outs, string dns = "">
let VM_CNT = 1;
let EXP_CNT = 1;
- let MIMG = 1;
+ let Format = AMDGPUInstrFormat.MIMG;
let Uses = [EXEC];
let mayLoad = 1;
let mayStore = 0;
@@ -379,8 +379,7 @@ class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
class VIMAGE<int op, dag outs, int num_addrs, Predicate pred,
MIMGEncoding encoding, string dns="", list<RegisterOperand> addr_types=[]>
: MIMG<outs, dns>, VIMAGEe<op> {
- let MIMG = 0;
- let VIMAGE = 1;
+ let Format = AMDGPUInstrFormat.VIMAGE;
let SubtargetPredicate = pred;
let AssemblerPredicate = pred;
@@ -403,8 +402,7 @@ class VIMAGE<int op, dag outs, int num_addrs, Predicate pred,
class VSAMPLE<int op, dag outs, int num_addrs, Predicate pred,
MIMGEncoding encoding, string dns="", RegisterOperand Addr3RC>
: MIMG<outs, dns>, VSAMPLEe<op> {
- let MIMG = 0;
- let VSAMPLE = 1;
+ let Format = AMDGPUInstrFormat.VSAMPLE;
let SubtargetPredicate = pred;
let AssemblerPredicate = pred;
@@ -2224,6 +2222,8 @@ class VIMAGE_TENSOR_Real <bits<8> op, VIMAGE_TENSOR_Pseudo ps, string opName = p
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
+ let Format = ps.Format;
+ let FormatModifier = ps.FormatModifier;
let TSFlags = ps.TSFlags;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index ace334c7b97b7..03921315144b6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -62,45 +62,22 @@ class InstSI <dag outs, dag ins, string asm = "",
field bit SALU = 0;
field bit VALU = 0;
- // SALU instruction formats.
- field bit SOP1 = 0;
- field bit SOP2 = 0;
- field bit SOPC = 0;
- field bit SOPK = 0;
- field bit SOPP = 0;
-
- // VALU instruction formats.
- field bit VOP1 = 0;
- field bit VOP2 = 0;
- field bit VOPC = 0;
- field bit VOP3 = 0;
- field bit VOP3P = 0;
- field bit VINTRP = 0;
- field bit SDWA = 0;
- field bit DPP = 0;
- field bit TRANS = 0;
+ // Mutually-exclusive instruction format, set directly by instruction classes.
+ field bits<5> Format = AMDGPUInstrFormat.NONE;
- // Memory instruction formats.
- field bit MUBUF = 0;
- field bit MTBUF = 0;
- field bit SMRD = 0;
- field bit MIMG = 0;
- field bit VIMAGE = 0;
- field bit VSAMPLE = 0;
- field bit EXP = 0;
- field bit FLAT = 0;
- field bit DS = 0;
-
- // Combined SGPR/VGPR spill bit
- field bit Spill = 0;
+ // Mutually-exclusive operand-encoding modifier (DPP/SDWA).
+ field bits<2> FormatModifier = AMDGPUFormatModifier.None;
- // LDSDIR instruction format.
- field bit LDSDIR = 0;
+ // Derived from Format (not part of TSFlags); only used as an instruction-
+ // relation-map key to tell the VOP3/e64 encoding apart from e32/sdwa/dpp.
+ bit IsVOP3Encoding = !eq(Format, AMDGPUInstrFormat.VOP3);
- // VINTERP instruction format.
- field bit VINTERP = 0;
+ // Derived from Format (not part of TSFlags); only used as a searchable-table
+ // key (VOPDPairs) to tell VOPD3 apart from the plain VOPD encoding.
+ bit VOPD3 = !eq(Format, AMDGPUInstrFormat.VOPD3);
- field bit VOPD3 = 0;
+ // Transcendental property flag (orthogonal to the format).
+ field bit TRANS = 0;
// High bits - other information.
field bit VM_CNT = 0;
@@ -201,40 +178,6 @@ class InstSI <dag outs, dag ins, string asm = "",
// This bit indicates that this is one of SWMMAC instructions.
field bit IsSWMMAC = 0;
- // Mutually-exclusive instruction format, derived from the format bits above.
- // The base format bits are all exclusive, so they collapse into one enum
- // field. VOP3P/VINTERP also set the VOP3 bit, so match them before VOP3.
- bits<5> Format = !cond(SOP1 : AMDGPUInstrFormat.SOP1,
- SOP2 : AMDGPUInstrFormat.SOP2,
- SOPC : AMDGPUInstrFormat.SOPC,
- SOPK : AMDGPUInstrFormat.SOPK,
- SOPP : AMDGPUInstrFormat.SOPP,
- VOP1 : AMDGPUInstrFormat.VOP1,
- VOP2 : AMDGPUInstrFormat.VOP2,
- VOPC : AMDGPUInstrFormat.VOPC,
- VOP3P : AMDGPUInstrFormat.VOP3P,
- VINTERP : AMDGPUInstrFormat.VINTERP,
- VOP3 : AMDGPUInstrFormat.VOP3,
- VINTRP : AMDGPUInstrFormat.VINTRP,
- VOPD3 : AMDGPUInstrFormat.VOPD3,
- LDSDIR : AMDGPUInstrFormat.LDSDIR,
- MUBUF : AMDGPUInstrFormat.MUBUF,
- MTBUF : AMDGPUInstrFormat.MTBUF,
- SMRD : AMDGPUInstrFormat.SMRD,
- MIMG : AMDGPUInstrFormat.MIMG,
- VIMAGE : AMDGPUInstrFormat.VIMAGE,
- VSAMPLE : AMDGPUInstrFormat.VSAMPLE,
- EXP : AMDGPUInstrFormat.EXP,
- FLAT : AMDGPUInstrFormat.FLAT,
- DS : AMDGPUInstrFormat.DS,
- Spill : AMDGPUInstrFormat.Spill,
- true : AMDGPUInstrFormat.NONE);
-
- // Mutually-exclusive operand-encoding modifier (DPP and SDWA never co-occur).
- bits<2> FormatModifier = !cond(DPP : AMDGPUFormatModifier.DPP,
- SDWA : AMDGPUFormatModifier.SDWA,
- true : AMDGPUFormatModifier.None);
-
let TSFlags{4-0} = Format;
let TSFlags{6-5} = FormatModifier;
@@ -302,7 +245,12 @@ class InstSI <dag outs, dag ins, string asm = "",
let AsmVariantName = AMDGPUAsmVariants.Default;
// Avoid changing source registers in a way that violates constant bus read limitations.
- let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
+ let hasExtraSrcRegAllocReq = !or(!eq(Format, AMDGPUInstrFormat.VOP1),
+ !eq(Format, AMDGPUInstrFormat.VOP2),
+ !eq(Format, AMDGPUInstrFormat.VOPC),
+ !eq(Format, AMDGPUInstrFormat.VOP3),
+ !eq(FormatModifier, AMDGPUFormatModifier.SDWA),
+ VALU);
}
class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
@@ -586,7 +534,7 @@ let Uses = [EXEC] in {
class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
- let VINTRP = 1;
+ let Format = AMDGPUInstrFormat.VINTRP;
// VINTRP instructions read parameter values from LDS, but these parameter
// values are stored outside of the LDS memory that is allocated to the
// shader for general purpose use.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 1df90ebbe9216..b44d2782e0d33 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3377,7 +3377,7 @@ multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
def getVOPe64 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
- let ColFields = ["Size", "VOP3"];
+ let ColFields = ["Size", "IsVOP3Encoding"];
let KeyCol = ["4", "0"];
let ValueCols = [["8", "1"]];
}
@@ -3386,7 +3386,7 @@ def getVOPe64 : InstrMapping {
def getVOPe32 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
- let ColFields = ["Size", "VOP3"];
+ let ColFields = ["Size", "IsVOP3Encoding"];
let KeyCol = ["8", "1"];
let ValueCols = [["4", "0"]];
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e891ba31bbf67..fe780ffb84f16 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -138,7 +138,7 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
let isMoveImm = 1;
let SchedRW = [Write64Bit];
let Size = 4;
- let VOP1 = 1; // Not entirely correct, but close enough.
+ let Format = AMDGPUInstrFormat.VOP1; // Not entirely correct, but close enough.
let UseNamedOperandTable = 1;
}
@@ -154,7 +154,7 @@ def AV_MOV_B32_IMM_PSEUDO
// Imprecise, technically if AGPR it's VOP3 and VOP1 for VGPR. But
// this tricks the rematerialize logic into working for it.
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let isMoveImm = 1;
let SchedRW = [Write32Bit];
let Size = 8;
@@ -173,7 +173,7 @@ def AV_MOV_B64_IMM_PSEUDO
// Imprecise, technically if AGPR it's 2 x VOP3 and 2 x VOP1 for
// VGPR. But this tricks the rematerialize logic into working for
// it.
- let VOP3 = 1;
+ let Format = AMDGPUInstrFormat.VOP3;
let isMoveImm = 1;
let SchedRW = [Write32Bit, Write32Bit];
let Size = 16; // 2 x v_accwrite_write_b32 in the worst case
@@ -517,7 +517,7 @@ class WrapTerminatorVOPC<VOPC_Pseudo base_inst> : VPseudoInstSI<
let isTerminator = 1;
let isConvergent = 1;
let isCompare = 1;
- let VOPC = 1;
+ let Format = AMDGPUInstrFormat.VOPC;
}
let SubtargetPredicate = HasNoSdstCMPX in {
@@ -1076,7 +1076,7 @@ class INDIRECT_REG_WRITE_MOVREL_pseudo<RegisterClass rc,
class V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<RegisterClass rc> :
INDIRECT_REG_WRITE_MOVREL_pseudo<rc, VSrc_b32> {
let VALU = 1;
- let VOP1 = 1;
+ let Format = AMDGPUInstrFormat.VOP1;
let Uses = [M0, EXEC];
}
@@ -1084,7 +1084,7 @@ class S_INDIRECT_REG_WRITE_MOVREL_pseudo<RegisterClass rc,
RegisterOperand val_ty> :
INDIRECT_REG_WRITE_MOVREL_pseudo<rc, val_ty> {
let SALU = 1;
- let SOP1 = 1;
+ let Format = AMDGPUInstrFormat.SOP1;
let Uses = [M0];
}
@@ -1180,7 +1180,7 @@ def V_INDIRECT_REG_READ_GPR_IDX_B32_V16 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VRe
def V_INDIRECT_REG_READ_GPR_IDX_B32_V32 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_1024>;
multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
- let UseNamedOperandTable = 1, Spill = 1, SALU = 1, Uses = [EXEC] in {
+ let UseNamedOperandTable = 1, Format = AMDGPUInstrFormat.Spill, SALU = 1, Uses = [EXEC] in {
def _SAVE : PseudoInstSI <
(outs),
(ins sgpr_class:$data, i32imm:$addr)> {
@@ -1221,7 +1221,7 @@ defm SI_SPILL_S384 : SI_SPILL_SGPR <SReg_384>;
defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
defm SI_SPILL_S1024 : SI_SPILL_SGPR <SReg_1024>;
-let Spill = 1, VALU = 1, isConvergent = 1 in {
+let Format = AMDGPUInstrFormat.Spill, VALU = 1, isConvergent = 1 in {
def SI_SPILL_S32_TO_VGPR : PseudoInstSI <(outs VGPR_32:$vdst),
(ins SReg_32:$src0, i32imm:$src1, VGPR_32:$vdst_in)> {
let Size = 4;
@@ -1243,14 +1243,14 @@ def SI_RESTORE_S32_FROM_VGPR : PseudoInstSI <(outs SReg_32:$sdst),
let mayStore = 0;
let hasExtraSrcRegAllocReq = 1;
}
-} // End Spill = 1, VALU = 1, isConvergent = 1
+} // End Format = AMDGPUInstrFormat.Spill, VALU = 1, isConvergent = 1
// VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
// needs to be used and an extra instruction to move between VGPR and AGPR.
// UsesTmp adds to the total size of an expanded spill in this case.
multiclass SI_SPILL_VGPR <SIRegisterClassLike vgpr_class,
bit UsesTmp = 0, bit HasMask = 0> {
- let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
+ let UseNamedOperandTable = 1, Format = AMDGPUInstrFormat.Spill, VALU = 1,
SchedRW = [WriteVMEM] in {
def _SAVE : VPseudoInstSI <
(outs),
@@ -1293,7 +1293,7 @@ multiclass SI_SPILL_VGPR <SIRegisterClassLike vgpr_class,
// Size field is unsigned char and cannot fit more.
let Size = !if(!le(MaxSize, 256), MaxSize, 252);
}
- } // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
+ } // End UseNamedOperandTable = 1, Format = AMDGPUInstrFormat.Spill, VALU = 1, SchedRW = [WriteVMEM]
}
// TODO: Technically the AlignTarget register class constraint is
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 19aeafe9b30cc..ec4422d2d484b 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -33,7 +33,7 @@ class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
let isCodeGenOnly = 1;
let LGKM_CNT = 1;
- let SMRD = 1;
+ let Format = AMDGPUInstrFormat.SMRD;
let mayStore = 0;
let mayLoad = 1;
let hasSideEffects = 0;
@@ -63,7 +63,6 @@ class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
// copy relevant pseudo op flags
let LGKM_CNT = ps.LGKM_CNT;
- let SMRD = ps.SMRD;
let mayStore = ps.mayStore;
let mayLoad = ps.mayLoad;
let hasSideEffects = ps.hasSideEffects;
@@ -77,7 +76,8 @@ class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
let Uses = ps.Uses;
let Defs = ps.D...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223785
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