[llvm-branch-commits] [llvm] [AMDGPU][SIInstrInfo] Materialise t16 PHI subreg operands (PR #222155)

[Shilei Tian via llvm-branch-commits]

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@@ -8097,8 +8095,16 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI, unsigned OpIdx,
   if (!RI.isVGPRClass(CurrRC))
     return;
 
-  int16_t RCID = getOpRegClassID(get(Opcode).operands()[OpIdx]);
-  const TargetRegisterClass *ExpectedRC = RI.getRegClass(RCID);
+  const TargetRegisterClass *ExpectedRC;
+  if (MI.isPHI()) {
+    // A PHI is generic, so it carries no operand register classes.
+    ExpectedRC = MRI.getRegClass(MI.getOperand(0).getReg());
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shiltian wrote:

>From MIR tests it does seem like PHI carries RC?

```
[[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[DEF]].hi16, %bb.1
```

https://github.com/llvm/llvm-project/pull/222155