[llvm-branch-commits] [llvm] [AMDGPU][SIInstrInfo] Materialise t16 PHI subreg operands (PR #222155)

Shilei Tian via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Sep 9 07:51:09 PDT 2026


================
@@ -8097,8 +8095,16 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI, unsigned OpIdx,
   if (!RI.isVGPRClass(CurrRC))
     return;
 
-  int16_t RCID = getOpRegClassID(get(Opcode).operands()[OpIdx]);
-  const TargetRegisterClass *ExpectedRC = RI.getRegClass(RCID);
+  const TargetRegisterClass *ExpectedRC;
----------------
shiltian wrote:

```suggestion
  const TargetRegisterClass *ExpectedRC = nullptr;
```

LLVM recently has a trend to always initialize local variables.

https://github.com/llvm/llvm-project/pull/222155


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