[llvm-branch-commits] [llvm] [AMDGPU] Machine verifier size check for 16bit register (PR #219734)

[Matt Arsenault via llvm-branch-commits]

================
@@ -5290,9 +5290,78 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
     ErrInfo = "illegal copy from vector register to SGPR";
     return false;
   }
+  // check for sreg32/vgpr3/vgpr16 mismatch
+  unsigned DstSubReg = MI.getOperand(0).getSubReg();
+  unsigned SrcSubReg = MI.getOperand(1).getSubReg();
+  auto *TRI = MRI.getTargetRegisterInfo();
+
+  if (RI.isAGPR(MRI, DstReg) || RI.isAGPR(MRI, SrcReg))
+    return true;
+
+  if (!DstReg.isVirtual() || !SrcReg.isVirtual())
+    return true;
+
+  auto *DstRC = getOpRegClass(MI, 0);
+  if (DstSubReg != AMDGPU::NoSubRegister)
+    DstRC = TRI->getSubRegisterClass(DstRC, DstSubReg);
+
+  auto *SrcRC = getOpRegClass(MI, 1);
+  if (SrcSubReg != AMDGPU::NoSubRegister)
+    SrcRC = TRI->getSubRegisterClass(SrcRC, SrcSubReg);
+
+  DstRC = RI.getEquivalentVGPRClass(DstRC);
+  SrcRC = RI.getEquivalentVGPRClass(SrcRC);
+  if (RI.getMatchingSuperRegClass(SrcRC, DstRC, AMDGPU::lo16) ||
+      RI.getMatchingSuperRegClass(DstRC, SrcRC, AMDGPU::lo16)) {
+    ErrInfo = "illegal copy with different size src/dst reg";
+    return false;
+  }
+
+  return true;
+}
+
+bool SIInstrInfo::verifyRegsequence(const MachineInstr &MI,
----------------
arsenm wrote:

```suggestion
bool SIInstrInfo::verifyRegSequence(const MachineInstr &MI,
```

https://github.com/llvm/llvm-project/pull/219734