[llvm-branch-commits] [llvm] [AMDGPU] Machine verifier size check for 16bit register (PR #219734)

[Matt Arsenault via llvm-branch-commits]

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@@ -5290,9 +5290,78 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
     ErrInfo = "illegal copy from vector register to SGPR";
     return false;
   }
+  // check for sreg32/vgpr3/vgpr16 mismatch
+  unsigned DstSubReg = MI.getOperand(0).getSubReg();
+  unsigned SrcSubReg = MI.getOperand(1).getSubReg();
+  auto *TRI = MRI.getTargetRegisterInfo();
+
+  if (RI.isAGPR(MRI, DstReg) || RI.isAGPR(MRI, SrcReg))
+    return true;
+
+  if (!DstReg.isVirtual() || !SrcReg.isVirtual())
+    return true;
+
+  auto *DstRC = getOpRegClass(MI, 0);
+  if (DstSubReg != AMDGPU::NoSubRegister)
+    DstRC = TRI->getSubRegisterClass(DstRC, DstSubReg);
+
+  auto *SrcRC = getOpRegClass(MI, 1);
+  if (SrcSubReg != AMDGPU::NoSubRegister)
+    SrcRC = TRI->getSubRegisterClass(SrcRC, SrcSubReg);
+
+  DstRC = RI.getEquivalentVGPRClass(DstRC);
+  SrcRC = RI.getEquivalentVGPRClass(SrcRC);
+  if (RI.getMatchingSuperRegClass(SrcRC, DstRC, AMDGPU::lo16) ||
+      RI.getMatchingSuperRegClass(DstRC, SrcRC, AMDGPU::lo16)) {
+    ErrInfo = "illegal copy with different size src/dst reg";
+    return false;
+  }
+
+  return true;
+}
+
+bool SIInstrInfo::verifyRegsequence(const MachineInstr &MI,
+                                    const MachineRegisterInfo &MRI,
+                                    StringRef &ErrInfo) const {
+  auto *TRI = MRI.getTargetRegisterInfo();
+  auto *SuperClass = getOpRegClass(MI, 0);
+  if (RI.isAGPR(MRI, MI.getOperand(0).getReg()))
+    return true;
+  for (int I = 1, E = MI.getNumOperands(); I != E; I += 2) {
+    auto *OpClass = getOpRegClass(MI, I);
+    unsigned SubReg = MI.getOperand(I).getSubReg();
+    if (MI.getOperand(I).isUndef() || RI.isAGPR(MRI, MI.getOperand(I).getReg()))
+      continue;
+    const TargetRegisterClass *SubClass;
+    if (SubReg != AMDGPU::NoSubRegister)
+      SubClass = TRI->getSubRegisterClass(OpClass, SubReg);
+    else
+      SubClass = OpClass;
+
+    SuperClass = RI.getEquivalentVGPRClass(SuperClass);
+    SubClass = RI.getEquivalentVGPRClass(SubClass);
+    if (!TRI->getMatchingSuperRegClass(SuperClass, SubClass,
+                                       MI.getOperand(I + 1).getImm())) {
+      ErrInfo = "illegal sub register in reg_sequence";
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arsenm wrote:

This stuff is already caught by the generic verifier?

https://github.com/llvm/llvm-project/pull/219734