[llvm-branch-commits] [llvm] [2/3][AMDGPU] Physical register tracking in GCN trackers (PR #184275)

[Dhruva Chakrabarti via llvm-branch-commits]

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@@ -7881,182 +7881,182 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT:    v_mov_b32_e32 v18, 0x7f
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dhruvachak wrote:

Scope: 
confined to v_fshr_v2i128. GFX10/11 unchanged.

Impact:
GFX6: 28 VGPRs → 28 VGPRs (reorder only).
GFX8: 28 VGPRs → 28 VGPRs (reorder only).
GFX9: 27 VGPRs → 28 VGPRs.
Occupancy: unchanged on all targets. GFX9 allocates VGPRs in 4-register granules, so 27 and 28 both round to a 28-VGPR allocation → occupancy 9 before and after. No spills.

Mechanism (GFX9): identical to the ABI-physreg pressure effect described for fshl.ll. v_fshr_v2i128 is a non-kernel function whose single region carries physical ABI VGPRs (24 argument live-ins, 8 return live-outs). These fold into the region pressure and raise the tracked peak from 28 to 34 VGPRs, lowering the scheduler's computed occupancy from 9 to 7. With the lower target the scheduler stops minimizing VGPRs and picks an order that register allocation colors with 28 instead of 27. The 34-VGPR peak is transient (the ABI registers are reused by allocation), so final occupancy stays at 9. In fshl.ll the same effect lands one VGPR lower; here it lands one higher.

https://github.com/llvm/llvm-project/pull/184275