[llvm-branch-commits] [llvm] [2/3][AMDGPU] Physical register tracking in GCN trackers (PR #184275)

[Dhruva Chakrabarti via llvm-branch-commits]

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@@ -8170,250 +8170,250 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
 ; GFX6-LABEL: v_fshl_v2i128:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_lshr_b64 v[23:24], v[8:9], 1
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dhruvachak wrote:

All changes are confined to v_fshl_v2i128 on GFX6/GFX8/GFX9 (GFX10/11 unchanged) and are a pure schedule/RA reshuffle. Net VGPR effect: GFX6 28→27, GFX8 28→27, GFX9 27→27 (reordered only).

Cause: physical-register pressure tracking. GCNScheduleDAGMILive::computeBlockPressure() always runs (even when the candidate GCN tracker is not used for scheduling) and now seeds physical live units, so region max-pressure and live-in/out sets include $vcc/SGPR condition registers. This feeds the pressure-aware scheduling and PreRA-rematerialization stages. v_fshl_v2i128 is sensitive because it has long $vcc carry chains (v_add/sub_i32_e32, v_cmp_*_e32, v_cndmask_e32) that were previously invisible to the pressure model.

Improvement: equal-or-better VGPR usage (−1 on GFX6/GFX8, unchanged elsewhere) from more accurate pressure modeling.

https://github.com/llvm/llvm-project/pull/184275