[llvm-branch-commits] [llvm] TableGen: Skip disjoint register classes before intersecting them (PR #234803)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/234803

inferCommonSubClass intersects the member lists of a register class
with every other class, and most pairs are disjoint. Check that with
the member bit vectors first, which avoids loading the members and
allocating the intersection.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    576               346            111
  After     573 (-0.6%)       343 (-0.7%)    110 (-0.6%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>

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>From eb5d3e27a25452ff955fe348e790585508a82a92 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 22 Oct 2026 14:19:45 -0700
Subject: [PATCH] TableGen: Skip disjoint register classes before intersecting
 them

inferCommonSubClass intersects the member lists of a register class
with every other class, and most pairs are disjoint. Check that with
the member bit vectors first, which avoids loading the members and
allocating the intersection.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    576               346            111
  After     573 (-0.6%)       343 (-0.7%)    110 (-0.6%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 0cbd1855429e3..c5fde00045e0b 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2530,6 +2530,10 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
     if (RC1 == RC2)
       continue;
 
+    // Skip disjoint class pairs, without loading the members.
+    if (!RC1->getMemberBV().anyCommon(RC2->getMemberBV()))
+      continue;
+
     // Compute the set intersection of RC1 and RC2.
     const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
     const CodeGenRegister::Vec &Memb2 = RC2->getMembers();