[llvm-branch-commits] [llvm] TableGen: Store super-register class sets as bit vectors (PR #234798)

[Jay Foad via llvm-branch-commits]

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@@ -518,15 +521,19 @@ class CodeGenRegisterClass {
   // getSuperRegClasses - Returns a bit vector of all register classes
   // containing only SubIdx super-registers of this class.
   void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
-                          BitVector &Out) const;
+                          const CodeGenRegBank &RegBank, BitVector &Out) const;
 
   // addSuperRegClass - Add a class containing only SubIdx super-registers.
   void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
                         CodeGenRegisterClass *SuperRC) {
-    SuperRegClasses[SubIdx].insert(SuperRC);
+    BitVector &Supers = SuperRegClasses[SubIdx];
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jayfoad wrote:

Maybe `assert(CreationIndex != ~0u)` here to enforce that `setCreationIndex` has been called?

https://github.com/llvm/llvm-project/pull/234798