[llvm-branch-commits] [llvm] TableGen: Index registers by sub-register index enum value when inferring sub-classes (PR #234799)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

inferSubClassWithSubReg groups the members of a register class by each
of their sub-register indices, and looked up every index of every member
in a std::map. Sub-register indices are numbered densely, so use a
vector indexed by enum value instead. Also count the members once
instead of once per index.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    622               380            120
  After     604 (-3.0%)       367 (-3.4%)    115 (-3.7%)

Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>

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---
Full diff: https://github.com/llvm/llvm-project/pull/234799.diff


1 Files Affected:

- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+12-16) 


``````````diff
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 3b5451e0d32b5..8da432b6c11b5 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2556,33 +2556,29 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
 // form a register class.  Update RC->SubClassWithSubReg.
 //
 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
-  // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
-  using SubReg2SetMap = std::map<const CodeGenSubRegIndex *,
-                                 CodeGenRegister::Vec, deref<std::less<>>>;
+  // The set of registers in RC supporting each SubRegIndex, indexed by
+  // EnumValue.
+  std::vector<CodeGenRegister::Vec> SRSets(SubRegIndices.size() + 1);
 
   // Compute the set of registers supporting each SubRegIndex.
-  SubReg2SetMap SRSets;
+  size_t NumNonArtificial = 0;
   for (const CodeGenRegister *R : RC->getMembers()) {
     if (R->Artificial)
       continue;
-    CodeGenRegister::SubRegArrayRef SRM = R->getSubRegs();
-    for (auto [I, _] : SRM)
-      SRSets[I].push_back(R);
+    ++NumNonArtificial;
+    for (auto [I, _] : R->getSubRegs())
+      SRSets[I->EnumValue].push_back(R);
   }
 
   // Find matching classes for all SRSets entries.  Iterate in SubRegIndex
   // numerical order to visit synthetic indices last.
   for (const CodeGenSubRegIndex &SubIdx : SubRegIndices) {
-    SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
+    const CodeGenRegister::Vec &Set = SRSets[SubIdx.EnumValue];
     // Unsupported SubRegIndex. Skip it.
-    if (I == SRSets.end())
+    if (Set.empty())
       continue;
     // In most cases, all RC registers support the SubRegIndex.
-    auto IsNotArtificial = [](const CodeGenRegister *R) {
-      return !R->Artificial;
-    };
-    if (I->second.size() ==
-        (size_t)count_if(RC->getMembers(), IsNotArtificial)) {
+    if (Set.size() == NumNonArtificial) {
       RC->setSubClassWithSubReg(&SubIdx, RC);
       continue;
     }
@@ -2590,8 +2586,8 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
       continue;
     // This is a real subset.  See if we have a matching class.
     CodeGenRegisterClass *SubRC =
-        getOrCreateSubClass(RC, &I->second,
-                            RC->getName() + "_with_" + I->first->getName())
+        getOrCreateSubClass(RC, &Set,
+                            RC->getName() + "_with_" + SubIdx.getName())
             .first;
     RC->setSubClassWithSubReg(&SubIdx, SubRC);
   }

``````````

</details>


https://github.com/llvm/llvm-project/pull/234799