[llvm-branch-commits] [llvm] TableGen: Test register sub-classes with the member bit vectors (PR #234801)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/234801

computeSubClasses checks whether one register class contains another
for most pairs of classes, by walking both sorted member lists. That
reads every member register, which is slow for AMDGPU's 913 classes.
Each class already has a bit vector of its members, so compare those
instead.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    596               365            117
  After     577 (-3.1%)       353 (-3.4%)    112 (-3.7%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>

---

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>From f68fa89e12ff14028fba3b2fb4483e11c4dc160a Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 22 Oct 2026 13:02:20 -0700
Subject: [PATCH] TableGen: Test register sub-classes with the member bit
 vectors

computeSubClasses checks whether one register class contains another
for most pairs of classes, by walking both sorted member lists. That
reads every member register, which is slow for AMDGPU's 913 classes.
Each class already has a bit vector of its members, so compare those
instead.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    596               365            117
  After     577 (-3.1%)       353 (-3.4%)    112 (-3.7%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 5 ++++-
 llvm/utils/TableGen/Common/CodeGenRegisters.h   | 3 +++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index be3c81128e50f..1674db63afb72 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -987,8 +987,11 @@ bool CodeGenRegisterClass::Key::operator<(
 //
 static bool testSubClass(const CodeGenRegisterClass *A,
                          const CodeGenRegisterClass *B) {
+  // Compare the member bit vectors rather than the member lists, which would
+  // load every register.
   return A->RSI.isSubClassOf(B->RSI) &&
-         llvm::includes(A->getMembers(), B->getMembers(), deref<std::less<>>());
+         B->getMembers().size() <= A->getMembers().size() &&
+         !B->getMemberBV().test(A->getMemberBV());
 }
 
 /// Sorting predicate for register classes.  This provides a topological
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index b5cfa8e600aa8..8bc3447453acc 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -560,6 +560,9 @@ class CodeGenRegisterClass {
   // getOrder(0).
   const CodeGenRegister::Vec &getMembers() const { return Members; }
 
+  // The members as a bit vector indexed by CodeGenRegBank::getRegIndex().
+  const BitVector &getMemberBV() const { return MemberBV; }
+
   // Get a bit vector of TopoSigs of registers with super registers in this
   // register class.
   const BitVector &getRegsWithSuperRegsTopoSigs() const {