[llvm-branch-commits] [llvm] TableGen: Skip redundant addComposite calls for secondary sub-registers (PR #234800)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

computeSecondarySubRegs calls addComposite for every index of every new
sub-register, and almost all of these calls repeat a composition that
is already known. For AMDGPU, only about 15000 of 29.8 million calls add
anything. Skip the call if the composition is known and its result has
an offset in every mode, since it would do nothing.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    603               367            116
  After     595 (-1.3%)       362 (-1.2%)    115 (-1.0%)

Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>

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---
Full diff: https://github.com/llvm/llvm-project/pull/234800.diff


2 Files Affected:

- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+6) 
- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.h (+1-1) 


``````````diff
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 8da432b6c11b5..be3c81128e50f 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -539,6 +539,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
   }
 
   // Create sub-register index composition maps for the synthesized indices.
+  unsigned NumModes = RegBank.getHwModes().getNumModeIds();
   for (auto [NewIdx, NewSubReg] : NewSubRegs) {
     for (auto [SRI, SubReg] : NewSubReg->SubRegs) {
       CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg);
@@ -546,6 +547,11 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
         PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
                                               SubReg->getName() + " in " +
                                               getName());
+      // Most compositions were already added for registers with the same
+      // structure, and then addComposite has no effect.
+      if (CodeGenSubRegIndex *Known = NewIdx->compose(SRI);
+          Known && Known->hasOffsetInAllModes(NumModes))
+        continue;
       NewIdx->addComposite(SRI, SubIdx, RegBank.getHwModes());
     }
   }
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 4b58b8d844169..b5cfa8e600aa8 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -181,7 +181,6 @@ class CodeGenSubRegIndex {
     return this->EnumValue < RHS.EnumValue;
   }
 
-private:
   // Return true if Range has an offset in all NumModes modes. Offsets are
   // never cleared once set, so cache a true result.
   bool hasOffsetInAllModes(unsigned NumModes) {
@@ -195,6 +194,7 @@ class CodeGenSubRegIndex {
     return OffsetInAllModes;
   }
 
+private:
   bool OffsetInAllModes = false;
   CompMap Composed;
   // Composed indexed by the EnumValue of the first index, for compose().

``````````

</details>


https://github.com/llvm/llvm-project/pull/234800