[llvm-branch-commits] [llvm] [AMDGPU] Fix the packed F32 unpack window in SIPreEmitPeephole (PR #233721)

[Akash Dutta via llvm-branch-commits]

================
@@ -385,6 +385,58 @@ llvm::AMDGPU::CoExecInfo llvm::AMDGPU::getMFMACoExecInfo(unsigned Opcode) {
   }
 }
 
+static unsigned getMFMANumPasses(const MachineInstr &MFMA,
+                                 const SIInstrInfo &TII) {
+  unsigned NumPasses = TII.getRepeatRate(MFMA);
+  assert(NumPasses >= 2 && "MFMA has no pass count in the scheduling model");
+  return NumPasses;
+}
+
+static unsigned getMFMASrcSize(const MachineInstr &MFMA, AMDGPU::OpName Name,
+                               const SIInstrInfo &TII) {
+  unsigned Opc = MFMA.getOpcode();
+  return TII.getOpSize(Opc, AMDGPU::getNamedOperandIdx(Opc, Name));
+}
+
+unsigned llvm::AMDGPU::getVALUIssueCycle(const MachineInstr &MFMA,
+                                         const SIInstrInfo &TII) {
+  assert(TII.getSubtarget().hasGFX940Insts() && SIInstrInfo::isMFMA(MFMA) &&
+         "expected a gfx942 or gfx950 MFMA");
+  if (!TII.isXDL(MFMA))
+    return getMFMANumPasses(MFMA, TII) + 2;
----------------
akadutta wrote:

I won't be the final approver on this. But can you point to the ISA or other docs for this instead of ATT? Hard coded constraints derived from the spec is maybe better than experimentally identified constraints.

https://github.com/llvm/llvm-project/pull/233721