[llvm-branch-commits] [llvm] [LoongArch] Add support for vector add/sub on vNi128 types (PR #193912)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 14 05:21:55 PDT 2026
https://github.com/heiher updated https://github.com/llvm/llvm-project/pull/193912
>From a525c673c8282df477deab1e504e90af533400eb Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Wed, 14 Oct 2026 17:48:23 +0800
Subject: [PATCH] [LoongArch] Add support for vector add/sub on vNi128 types
Make v1i128 and v2i128 legal types in the LSX/LASX register classes and
lower ADD/SUB on them to VADD.Q/XVADD.Q and VSUB.Q/XVSUB.Q.
The vNi128 types are intentionally kept out of LSXVTs/LASXVTs so that
only a minimal set of operations is legal on them: LOAD, STORE, BITCAST,
UNDEF, ADD, SUB and VSELECT (via [X]VBITSEL.V). VECTOR_SHUFFLE is custom
lowered by performing the shuffle on the equivalent i64 vector type.
Everything else keeps the default Expand action.
Since the widening extend combine can now produce VEXTH/VEXTH_U on
vNi128, also add the [X]VEXTH.Q.D and [X]VEXTH.QU.DU patterns.
---
.../LoongArch/LoongArchISelLowering.cpp | 40 +-
.../LoongArch/LoongArchLASXInstrInfo.td | 33 +-
.../Target/LoongArch/LoongArchLSXInstrInfo.td | 33 +-
.../Target/LoongArch/LoongArchRegisterInfo.td | 4 +-
.../LoongArch/lasx/ir-instruction/add.ll | 100 +----
.../LoongArch/lasx/ir-instruction/sub.ll | 106 +----
llvm/test/CodeGen/LoongArch/lasx/vec-i128.ll | 364 +++++++----------
llvm/test/CodeGen/LoongArch/lasx/xvexth.ll | 72 +---
.../LoongArch/lsx/ir-instruction/add.ll | 57 +--
.../LoongArch/lsx/ir-instruction/sub.ll | 57 +--
llvm/test/CodeGen/LoongArch/lsx/vec-i128.ll | 384 +++++++++---------
llvm/test/CodeGen/LoongArch/lsx/vexth.ll | 52 +--
12 files changed, 500 insertions(+), 802 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 1d01e76a5ebd2d..994340da66672e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -94,13 +94,21 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
static const MVT::SimpleValueType LASXVTs[] = {
MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64};
- if (Subtarget.hasExtLSX())
+ if (Subtarget.hasExtLSX()) {
for (MVT VT : LSXVTs)
addRegisterClass(VT, &LoongArch::LSX128RegClass);
+ // v1i128 is only legal for a small set of operations (see below), so it
+ // is intentionally kept out of LSXVTs.
+ addRegisterClass(MVT::v1i128, &LoongArch::LSX128RegClass);
+ }
- if (Subtarget.hasExtLASX())
+ if (Subtarget.hasExtLASX()) {
for (MVT VT : LASXVTs)
addRegisterClass(VT, &LoongArch::LASX256RegClass);
+ // v2i128 is only legal for a small set of operations (see below), so it
+ // is intentionally kept out of LASXVTs.
+ addRegisterClass(MVT::v2i128, &LoongArch::LASX256RegClass);
+ }
// Set operations for LA32 and LA64.
@@ -411,6 +419,14 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
for (MVT VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v16i32, MVT::v8i64,
MVT::v16i64})
setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
+
+ // Only a minimal set of operations is legal on v1i128. Everything else
+ // keeps the default Expand action set above.
+ setOperationAction({ISD::LOAD, ISD::STORE}, MVT::v1i128, Legal);
+ setOperationAction({ISD::BITCAST, ISD::UNDEF}, MVT::v1i128, Legal);
+ setOperationAction(ISD::VSELECT, MVT::v1i128, Legal);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i128, Custom);
+ setOperationAction({ISD::ADD, ISD::SUB}, MVT::v1i128, Legal);
}
// Set operations for 'LASX' feature.
@@ -500,6 +516,14 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
}
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
setOperationAction(ISD::TRUNCATE, VT, Legal);
+
+ // Only a minimal set of operations is legal on v2i128. Everything else
+ // keeps the default Expand action set above.
+ setOperationAction({ISD::LOAD, ISD::STORE}, MVT::v2i128, Legal);
+ setOperationAction({ISD::BITCAST, ISD::UNDEF}, MVT::v2i128, Legal);
+ setOperationAction(ISD::VSELECT, MVT::v2i128, Legal);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i128, Custom);
+ setOperationAction({ISD::ADD, ISD::SUB}, MVT::v2i128, Legal);
}
// Set DAG combine for LA32 and LA64.
@@ -3538,6 +3562,18 @@ SDValue LoongArchTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
[&](int M) { return -1 <= M && M < MaskUpperLimit; }) &&
"Out of bounds shuffle index");
+ // There are no shuffle instructions on i128 elements, so perform the
+ // shuffle on the equivalent i64 vector type instead.
+ if (VT.getVectorElementType() == MVT::i128) {
+ MVT NewVT = MVT::getVectorVT(MVT::i64, NumElements * 2);
+ SmallVector<int, 8> NewMask;
+ narrowShuffleMaskElts(2, OrigMask, NewMask);
+ SDValue NewShuffle =
+ DAG.getVectorShuffle(NewVT, DL, DAG.getBitcast(NewVT, V1),
+ DAG.getBitcast(NewVT, V2), NewMask);
+ return DAG.getBitcast(VT, NewShuffle);
+ }
+
// For each vector width, delegate to a specialized lowering routine.
if (VT.is128BitVector())
return lower128BitShuffle(DL, OrigMask, VT, V1, V2, DAG, Subtarget);
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index fcd134770332de..992a0213b7da01 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1142,6 +1142,8 @@ multiclass PatXrW<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_W_H") LASX256:$vj)>;
def : Pat<(v4i64 (OpNode(v8i32 LASX256:$vj))),
(!cast<LAInst>(Inst#"_D_W") LASX256:$vj)>;
+ def : Pat<(v2i128 (OpNode(v4i64 LASX256:$vj))),
+ (!cast<LAInst>(Inst#"_Q_D") LASX256:$vj)>;
}
multiclass PatXrWU<SDPatternOperator OpNode, string Inst> {
@@ -1151,6 +1153,8 @@ multiclass PatXrWU<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_WU_HU") LASX256:$vj)>;
def : Pat<(v4i64 (OpNode(v8i32 LASX256:$vj))),
(!cast<LAInst>(Inst#"_DU_WU") LASX256:$vj)>;
+ def : Pat<(v2i128 (OpNode(v4i64 LASX256:$vj))),
+ (!cast<LAInst>(Inst#"_QU_DU") LASX256:$vj)>;
}
multiclass PatXrXr<SDPatternOperator OpNode, string Inst> {
@@ -1171,6 +1175,19 @@ multiclass PatXrXrF<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
}
+multiclass PatXrXrQ<SDPatternOperator OpNode, string Inst> {
+ def : Pat<(OpNode (v32i8 LASX256:$xj), (v32i8 LASX256:$xk)),
+ (!cast<LAInst>(Inst#"_B") LASX256:$xj, LASX256:$xk)>;
+ def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 LASX256:$xk)),
+ (!cast<LAInst>(Inst#"_H") LASX256:$xj, LASX256:$xk)>;
+ def : Pat<(OpNode (v8i32 LASX256:$xj), (v8i32 LASX256:$xk)),
+ (!cast<LAInst>(Inst#"_W") LASX256:$xj, LASX256:$xk)>;
+ def : Pat<(OpNode (v4i64 LASX256:$xj), (v4i64 LASX256:$xk)),
+ (!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
+ def : Pat<(OpNode (v2i128 LASX256:$xj), (v2i128 LASX256:$xk)),
+ (!cast<LAInst>(Inst#"_Q") LASX256:$xj, LASX256:$xk)>;
+}
+
multiclass PatXrXrU<SDPatternOperator OpNode, string Inst> {
def : Pat<(OpNode (v32i8 LASX256:$xj), (v32i8 LASX256:$xk)),
(!cast<LAInst>(Inst#"_BU") LASX256:$xj, LASX256:$xk)>;
@@ -1394,10 +1411,10 @@ multiclass PairInsertExtractPatV4<ValueType vecty, ValueType elemty> {
let Predicates = [HasExtLASX] in {
-// XVADD_{B/H/W/D}
-defm : PatXrXr<add, "XVADD">;
-// XVSUB_{B/H/W/D}
-defm : PatXrXr<sub, "XVSUB">;
+// XVADD_{B/H/W/D/Q}
+defm : PatXrXrQ<add, "XVADD">;
+// XVSUB_{B/H/W/D/Q}
+defm : PatXrXrQ<sub, "XVSUB">;
// XVADDI_{B/H/W/D}U
defm : PatXrNimm5<sub, "XVADDI">;
@@ -1540,10 +1557,10 @@ defm : PatXrUimmW<loongarch_vsllwil, "XVSLLWIL">;
// XVSLLWIL_{HU_BU/WU_HU/DU_WU}
defm : PatXrUimmWU<loongarch_vsllwil_u, "XVSLLWIL">;
-// VEXTH_{H_B/W_H/D_W}
+// VEXTH_{H_B/W_H/D_W/Q_D}
defm : PatXrW<loongarch_vexth, "XVEXTH">;
-// VEXTH_{HU_BU/WU_HU/DU_WU}
+// VEXTH_{HU_BU/WU_HU/DU_WU/QU_DU}
defm : PatXrWU<loongarch_vexth_u, "XVEXTH">;
// XVCLO_{B/H/W/D}
@@ -2093,7 +2110,7 @@ defm : VstelmPat<store, v8f32, XVSTELM_W, simm8_lsl2, uimm3, f32>;
defm : VstelmPat<store, v4f64, XVSTELM_D, simm8_lsl3, uimm2, f64>;
// Loads/Stores
-foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in {
+foreach vt = [v32i8, v16i16, v8i32, v4i64, v2i128, v8f32, v4f64] in {
defm : LdPat<load, XVLD, vt>;
def : RegRegLdPat<load, XVLDX, vt>;
defm : StPat<store, XVST, LASX256, vt>;
@@ -2164,7 +2181,7 @@ def : Pat<(f64(vector_extract v4f64:$xj, uimm2:$imm)),
def : Pat<(v32i8 (vselect LASX256:$xd, (v32i8 (SplatPat_uimm8 uimm8:$imm)),
LASX256:$xj)),
(XVBITSELI_B LASX256:$xd, LASX256:$xj, uimm8:$imm)>;
-foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in
+foreach vt = [v32i8, v16i16, v8i32, v4i64, v2i128, v8f32, v4f64] in
def : Pat<(vt (vselect LASX256:$xa, LASX256:$xk, LASX256:$xj)),
(XVBITSEL_V LASX256:$xj, LASX256:$xk, LASX256:$xa)>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index e1489f9e36d69b..fa8918da159560 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -1404,6 +1404,8 @@ multiclass PatVrW<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_W_H") LSX128:$vj)>;
def : Pat<(v2i64 (OpNode(v4i32 LSX128:$vj))),
(!cast<LAInst>(Inst#"_D_W") LSX128:$vj)>;
+ def : Pat<(v1i128 (OpNode(v2i64 LSX128:$vj))),
+ (!cast<LAInst>(Inst#"_Q_D") LSX128:$vj)>;
}
multiclass PatVrWU<SDPatternOperator OpNode, string Inst> {
@@ -1413,6 +1415,8 @@ multiclass PatVrWU<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_WU_HU") LSX128:$vj)>;
def : Pat<(v2i64 (OpNode(v4i32 LSX128:$vj))),
(!cast<LAInst>(Inst#"_DU_WU") LSX128:$vj)>;
+ def : Pat<(v1i128 (OpNode(v2i64 LSX128:$vj))),
+ (!cast<LAInst>(Inst#"_QU_DU") LSX128:$vj)>;
}
multiclass PatVrVr<SDPatternOperator OpNode, string Inst> {
@@ -1433,6 +1437,19 @@ multiclass PatVrVrF<SDPatternOperator OpNode, string Inst> {
(!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;
}
+multiclass PatVrVrQ<SDPatternOperator OpNode, string Inst> {
+ def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),
+ (!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>;
+ def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),
+ (!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>;
+ def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),
+ (!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>;
+ def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),
+ (!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;
+ def : Pat<(OpNode (v1i128 LSX128:$vj), (v1i128 LSX128:$vk)),
+ (!cast<LAInst>(Inst#"_Q") LSX128:$vj, LSX128:$vk)>;
+}
+
multiclass PatVrVrU<SDPatternOperator OpNode, string Inst> {
def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),
(!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>;
@@ -1670,10 +1687,10 @@ multiclass InsertExtractPatV2<ValueType vecty, ValueType elemty> {
let Predicates = [HasExtLSX] in {
-// VADD_{B/H/W/D}
-defm : PatVrVr<add, "VADD">;
-// VSUB_{B/H/W/D}
-defm : PatVrVr<sub, "VSUB">;
+// VADD_{B/H/W/D/Q}
+defm : PatVrVrQ<add, "VADD">;
+// VSUB_{B/H/W/D/Q}
+defm : PatVrVrQ<sub, "VSUB">;
// VADDI_{B/H/W/D}U
defm : PatVrNimm5<sub, "VADDI">;
@@ -1816,10 +1833,10 @@ defm : PatVrUimmW<loongarch_vsllwil, "VSLLWIL">;
// VSLLWIL_{HU_BU/WU_HU/DU_WU}
defm : PatVrUimmWU<loongarch_vsllwil_u, "VSLLWIL">;
-// VEXTH_{H_B/W_H/D_W}
+// VEXTH_{H_B/W_H/D_W/Q_D}
defm : PatVrW<loongarch_vexth, "VEXTH">;
-// VEXTH_{HU_BU/WU_HU/DU_WU}
+// VEXTH_{HU_BU/WU_HU/DU_WU/QU_DU}
defm : PatVrWU<loongarch_vexth_u, "VEXTH">;
// VCLO_{B/H/W/D}
@@ -2321,7 +2338,7 @@ defm : VstelmPat<store, v4f32, VSTELM_W, simm8_lsl2, uimm2, f32>;
defm : VstelmPat<store, v2f64, VSTELM_D, simm8_lsl3, uimm1, f64>;
// Loads/Stores
-foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
+foreach vt = [v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64] in {
defm : LdPat<load, VLD, vt>;
def : RegRegLdPat<load, VLDX, vt>;
defm : StPat<store, VST, LSX128, vt>;
@@ -2389,7 +2406,7 @@ def : Pat<(f64 (vector_extract v2f64:$vj, GRLenVT:$rk)),
def : Pat<(v16i8 (vselect LSX128:$vd, (v16i8 (SplatPat_uimm8 uimm8:$imm)),
LSX128:$vj)),
(VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>;
-foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
+foreach vt = [v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64] in
def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)),
(VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
index 2a8cdf953e00f4..8008e3a218e3b6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
@@ -202,7 +202,7 @@ def VR#I : LoongArchReg128<!cast<LoongArchReg64>("F"#I#"_64"), "vr"#I>,
DwarfRegAlias<!cast<LoongArchReg64>("F"#I#"_64")>;
def LSX128 : RegisterClass<"LoongArch",
- [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
+ [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, v1i128],
128, (sequence "VR%u", 0, 31)>;
// LASX registers
@@ -212,7 +212,7 @@ def XR#I : LoongArchReg256<!cast<LoongArchReg128>("VR"#I), "xr"#I>,
DwarfRegAlias<!cast<LoongArchReg128>("VR"#I)>;
def LASX256 : RegisterClass<"LoongArch",
- [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
+ [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64, v2i128],
256, (sequence "XR%u", 0, 31)>;
// Scratchpad registers
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
index 9043ed0b3eaed4..cfb64c95e5f9b8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @add_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: add_v32i8:
@@ -123,95 +123,13 @@ entry:
}
define void @add_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
-; LA32-LABEL: add_v2i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: addi.w $sp, $sp, -16
-; LA32-NEXT: st.w $fp, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT: ld.w $a3, $a1, 28
-; LA32-NEXT: ld.w $a4, $a1, 24
-; LA32-NEXT: ld.w $a5, $a1, 16
-; LA32-NEXT: ld.w $a6, $a1, 20
-; LA32-NEXT: ld.w $a7, $a1, 12
-; LA32-NEXT: ld.w $t0, $a1, 8
-; LA32-NEXT: ld.w $t1, $a1, 0
-; LA32-NEXT: ld.w $a1, $a1, 4
-; LA32-NEXT: ld.w $t2, $a2, 28
-; LA32-NEXT: ld.w $t3, $a2, 24
-; LA32-NEXT: ld.w $t4, $a2, 16
-; LA32-NEXT: ld.w $t5, $a2, 20
-; LA32-NEXT: ld.w $t6, $a2, 4
-; LA32-NEXT: ld.w $t7, $a2, 0
-; LA32-NEXT: ld.w $t8, $a2, 12
-; LA32-NEXT: ld.w $a2, $a2, 8
-; LA32-NEXT: add.w $t6, $a1, $t6
-; LA32-NEXT: add.w $t7, $t1, $t7
-; LA32-NEXT: sltu $t1, $t7, $t1
-; LA32-NEXT: add.w $t6, $t6, $t1
-; LA32-NEXT: sltu $fp, $t6, $a1
-; LA32-NEXT: xor $a1, $t6, $a1
-; LA32-NEXT: sltui $a1, $a1, 1
-; LA32-NEXT: masknez $fp, $fp, $a1
-; LA32-NEXT: maskeqz $a1, $t1, $a1
-; LA32-NEXT: or $a1, $a1, $fp
-; LA32-NEXT: add.w $a2, $t0, $a2
-; LA32-NEXT: add.w $a1, $a2, $a1
-; LA32-NEXT: sltu $t1, $a1, $a2
-; LA32-NEXT: add.w $a7, $a7, $t8
-; LA32-NEXT: sltu $a2, $a2, $t0
-; LA32-NEXT: add.w $a2, $a7, $a2
-; LA32-NEXT: add.w $a2, $a2, $t1
-; LA32-NEXT: add.w $a7, $a6, $t5
-; LA32-NEXT: add.w $t0, $a5, $t4
-; LA32-NEXT: sltu $a5, $t0, $a5
-; LA32-NEXT: add.w $a7, $a7, $a5
-; LA32-NEXT: sltu $t1, $a7, $a6
-; LA32-NEXT: xor $a6, $a7, $a6
-; LA32-NEXT: sltui $a6, $a6, 1
-; LA32-NEXT: masknez $t1, $t1, $a6
-; LA32-NEXT: maskeqz $a5, $a5, $a6
-; LA32-NEXT: or $a5, $a5, $t1
-; LA32-NEXT: add.w $a6, $a4, $t3
-; LA32-NEXT: add.w $a5, $a6, $a5
-; LA32-NEXT: sltu $t1, $a5, $a6
-; LA32-NEXT: add.w $a3, $a3, $t2
-; LA32-NEXT: sltu $a4, $a6, $a4
-; LA32-NEXT: add.w $a3, $a3, $a4
-; LA32-NEXT: add.w $a3, $a3, $t1
-; LA32-NEXT: st.w $t0, $a0, 16
-; LA32-NEXT: st.w $t7, $a0, 0
-; LA32-NEXT: st.w $a7, $a0, 20
-; LA32-NEXT: st.w $t6, $a0, 4
-; LA32-NEXT: st.w $a5, $a0, 24
-; LA32-NEXT: st.w $a1, $a0, 8
-; LA32-NEXT: st.w $a3, $a0, 28
-; LA32-NEXT: st.w $a2, $a0, 12
-; LA32-NEXT: ld.w $fp, $sp, 12 # 4-byte Folded Reload
-; LA32-NEXT: addi.w $sp, $sp, 16
-; LA32-NEXT: ret
-;
-; LA64-LABEL: add_v2i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 16
-; LA64-NEXT: ld.d $a4, $a1, 24
-; LA64-NEXT: ld.d $a5, $a1, 0
-; LA64-NEXT: ld.d $a1, $a1, 8
-; LA64-NEXT: ld.d $a6, $a2, 8
-; LA64-NEXT: ld.d $a7, $a2, 0
-; LA64-NEXT: ld.d $t0, $a2, 16
-; LA64-NEXT: ld.d $a2, $a2, 24
-; LA64-NEXT: add.d $a1, $a1, $a6
-; LA64-NEXT: add.d $a6, $a5, $a7
-; LA64-NEXT: sltu $a5, $a6, $a5
-; LA64-NEXT: add.d $a1, $a1, $a5
-; LA64-NEXT: add.d $a2, $a4, $a2
-; LA64-NEXT: add.d $a4, $a3, $t0
-; LA64-NEXT: sltu $a3, $a4, $a3
-; LA64-NEXT: add.d $a2, $a2, $a3
-; LA64-NEXT: st.d $a4, $a0, 16
-; LA64-NEXT: st.d $a6, $a0, 0
-; LA64-NEXT: st.d $a2, $a0, 24
-; LA64-NEXT: st.d $a1, $a0, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: add_v2i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvadd.q $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v0 = load <2 x i128>, ptr %a0
%v1 = load <2 x i128>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
index 505ae00f69cbdc..ee23370e994522 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @sub_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: sub_v32i8:
@@ -67,101 +67,13 @@ entry:
}
define void @sub_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
-; LA32-LABEL: sub_v2i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: addi.w $sp, $sp, -16
-; LA32-NEXT: st.w $fp, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s0, $sp, 8 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s1, $sp, 4 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s2, $sp, 0 # 4-byte Folded Spill
-; LA32-NEXT: ld.w $a3, $a1, 28
-; LA32-NEXT: ld.w $a4, $a1, 24
-; LA32-NEXT: ld.w $a5, $a1, 16
-; LA32-NEXT: ld.w $a6, $a1, 20
-; LA32-NEXT: ld.w $a7, $a1, 12
-; LA32-NEXT: ld.w $t0, $a1, 8
-; LA32-NEXT: ld.w $t1, $a1, 0
-; LA32-NEXT: ld.w $a1, $a1, 4
-; LA32-NEXT: ld.w $t2, $a2, 28
-; LA32-NEXT: ld.w $t3, $a2, 24
-; LA32-NEXT: ld.w $t4, $a2, 16
-; LA32-NEXT: ld.w $t5, $a2, 20
-; LA32-NEXT: ld.w $t6, $a2, 4
-; LA32-NEXT: ld.w $t7, $a2, 12
-; LA32-NEXT: ld.w $t8, $a2, 8
-; LA32-NEXT: ld.w $a2, $a2, 0
-; LA32-NEXT: sltu $fp, $a1, $t6
-; LA32-NEXT: xor $s0, $a1, $t6
-; LA32-NEXT: sltui $s0, $s0, 1
-; LA32-NEXT: masknez $fp, $fp, $s0
-; LA32-NEXT: sltu $s1, $t1, $a2
-; LA32-NEXT: maskeqz $s0, $s1, $s0
-; LA32-NEXT: or $fp, $s0, $fp
-; LA32-NEXT: sub.w $s0, $t0, $t8
-; LA32-NEXT: sltu $s2, $s0, $fp
-; LA32-NEXT: sltu $t0, $t0, $t8
-; LA32-NEXT: sub.w $a7, $a7, $t7
-; LA32-NEXT: sub.w $a7, $a7, $t0
-; LA32-NEXT: sub.w $a7, $a7, $s2
-; LA32-NEXT: sltu $t0, $a6, $t5
-; LA32-NEXT: xor $t7, $a6, $t5
-; LA32-NEXT: sltui $t7, $t7, 1
-; LA32-NEXT: masknez $t0, $t0, $t7
-; LA32-NEXT: sltu $t8, $a5, $t4
-; LA32-NEXT: maskeqz $t7, $t8, $t7
-; LA32-NEXT: or $t0, $t7, $t0
-; LA32-NEXT: sub.w $t7, $a4, $t3
-; LA32-NEXT: sltu $s2, $t7, $t0
-; LA32-NEXT: sltu $a4, $a4, $t3
-; LA32-NEXT: sub.w $a3, $a3, $t2
-; LA32-NEXT: sub.w $a3, $a3, $a4
-; LA32-NEXT: sub.w $a3, $a3, $s2
-; LA32-NEXT: sub.w $a4, $s0, $fp
-; LA32-NEXT: sub.w $t0, $t7, $t0
-; LA32-NEXT: sub.w $a1, $a1, $t6
-; LA32-NEXT: sub.w $a1, $a1, $s1
-; LA32-NEXT: sub.w $a6, $a6, $t5
-; LA32-NEXT: sub.w $a6, $a6, $t8
-; LA32-NEXT: sub.w $a2, $t1, $a2
-; LA32-NEXT: sub.w $a5, $a5, $t4
-; LA32-NEXT: st.w $a5, $a0, 16
-; LA32-NEXT: st.w $a2, $a0, 0
-; LA32-NEXT: st.w $a6, $a0, 20
-; LA32-NEXT: st.w $a1, $a0, 4
-; LA32-NEXT: st.w $t0, $a0, 24
-; LA32-NEXT: st.w $a4, $a0, 8
-; LA32-NEXT: st.w $a3, $a0, 28
-; LA32-NEXT: st.w $a7, $a0, 12
-; LA32-NEXT: ld.w $s2, $sp, 0 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s1, $sp, 4 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s0, $sp, 8 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $fp, $sp, 12 # 4-byte Folded Reload
-; LA32-NEXT: addi.w $sp, $sp, 16
-; LA32-NEXT: ret
-;
-; LA64-LABEL: sub_v2i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 24
-; LA64-NEXT: ld.d $a4, $a1, 16
-; LA64-NEXT: ld.d $a5, $a1, 8
-; LA64-NEXT: ld.d $a1, $a1, 0
-; LA64-NEXT: ld.d $a6, $a2, 0
-; LA64-NEXT: ld.d $a7, $a2, 8
-; LA64-NEXT: ld.d $t0, $a2, 24
-; LA64-NEXT: ld.d $a2, $a2, 16
-; LA64-NEXT: sltu $t1, $a1, $a6
-; LA64-NEXT: sub.d $a5, $a5, $a7
-; LA64-NEXT: sub.d $a5, $a5, $t1
-; LA64-NEXT: sltu $a7, $a4, $a2
-; LA64-NEXT: sub.d $a3, $a3, $t0
-; LA64-NEXT: sub.d $a3, $a3, $a7
-; LA64-NEXT: sub.d $a1, $a1, $a6
-; LA64-NEXT: sub.d $a2, $a4, $a2
-; LA64-NEXT: st.d $a2, $a0, 16
-; LA64-NEXT: st.d $a1, $a0, 0
-; LA64-NEXT: st.d $a3, $a0, 24
-; LA64-NEXT: st.d $a5, $a0, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: sub_v2i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: xvsub.q $xr0, $xr0, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v0 = load <2 x i128>, ptr %a0
%v1 = load <2 x i128>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-i128.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-i128.ll
index 809285b6821f9e..7e7b53d37f16a6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-i128.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-i128.ll
@@ -18,29 +18,11 @@ entry:
}
define void @load_store_v2i128(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: load_store_v2i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: ld.w $a2, $a1, 24
-; LA32-NEXT: ld.w $a3, $a1, 28
-; LA32-NEXT: ld.w $a4, $a1, 16
-; LA32-NEXT: ld.w $a1, $a1, 20
-; LA32-NEXT: st.w $a2, $a0, 24
-; LA32-NEXT: st.w $a3, $a0, 28
-; LA32-NEXT: st.w $a4, $a0, 16
-; LA32-NEXT: st.w $a1, $a0, 20
-; LA32-NEXT: vst $vr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: load_store_v2i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a2, $a1, 16
-; LA64-NEXT: ld.d $a3, $a1, 24
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: st.d $a2, $a0, 16
-; LA64-NEXT: st.d $a3, $a0, 24
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: load_store_v2i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <2 x i128>, ptr %a
store <2 x i128> %v, ptr %res
@@ -50,73 +32,79 @@ entry:
define void @select_v1i128(ptr %res, ptr %a0, ptr %a1) nounwind {
; LA32-LABEL: select_v1i128:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a3, $a1, 0
-; LA32-NEXT: ld.w $a4, $a1, 4
-; LA32-NEXT: ld.w $a5, $a1, 8
-; LA32-NEXT: ld.w $a1, $a1, 12
-; LA32-NEXT: ld.w $a6, $a2, 12
-; LA32-NEXT: ld.w $a7, $a2, 0
-; LA32-NEXT: ld.w $t0, $a2, 4
-; LA32-NEXT: ld.w $a2, $a2, 8
-; LA32-NEXT: sltu $t1, $a1, $a6
-; LA32-NEXT: xor $t2, $a1, $a6
-; LA32-NEXT: sltui $t3, $t2, 1
-; LA32-NEXT: masknez $t1, $t1, $t3
-; LA32-NEXT: sltu $t4, $a5, $a2
-; LA32-NEXT: maskeqz $t3, $t4, $t3
-; LA32-NEXT: or $t1, $t3, $t1
-; LA32-NEXT: xor $t3, $a5, $a2
-; LA32-NEXT: or $t2, $t3, $t2
+; LA32-NEXT: vld $vr0, $a2, 0
+; LA32-NEXT: vld $vr1, $a1, 0
+; LA32-NEXT: vpickve2gr.w $a1, $vr0, 3
+; LA32-NEXT: vpickve2gr.w $a2, $vr1, 3
+; LA32-NEXT: sltu $a3, $a2, $a1
+; LA32-NEXT: xor $a4, $a2, $a1
+; LA32-NEXT: sltui $a5, $a4, 1
+; LA32-NEXT: masknez $a3, $a3, $a5
+; LA32-NEXT: vpickve2gr.w $a6, $vr0, 2
+; LA32-NEXT: vpickve2gr.w $a7, $vr1, 2
+; LA32-NEXT: sltu $t0, $a7, $a6
+; LA32-NEXT: maskeqz $a5, $t0, $a5
+; LA32-NEXT: or $a3, $a5, $a3
+; LA32-NEXT: xor $a5, $a7, $a6
+; LA32-NEXT: or $a4, $a5, $a4
+; LA32-NEXT: sltui $a4, $a4, 1
+; LA32-NEXT: masknez $a3, $a3, $a4
+; LA32-NEXT: vpickve2gr.w $a5, $vr0, 1
+; LA32-NEXT: vpickve2gr.w $t0, $vr1, 1
+; LA32-NEXT: sltu $t1, $t0, $a5
+; LA32-NEXT: xor $t2, $t0, $a5
; LA32-NEXT: sltui $t2, $t2, 1
; LA32-NEXT: masknez $t1, $t1, $t2
-; LA32-NEXT: sltu $t3, $a4, $t0
-; LA32-NEXT: xor $t4, $a4, $t0
-; LA32-NEXT: sltui $t4, $t4, 1
-; LA32-NEXT: masknez $t3, $t3, $t4
-; LA32-NEXT: sltu $t5, $a3, $a7
-; LA32-NEXT: maskeqz $t4, $t5, $t4
-; LA32-NEXT: or $t3, $t4, $t3
-; LA32-NEXT: maskeqz $t2, $t3, $t2
+; LA32-NEXT: vpickve2gr.w $t3, $vr0, 0
+; LA32-NEXT: vpickve2gr.w $t4, $vr1, 0
+; LA32-NEXT: sltu $t5, $t4, $t3
+; LA32-NEXT: maskeqz $t2, $t5, $t2
; LA32-NEXT: or $t1, $t2, $t1
-; LA32-NEXT: masknez $t0, $t0, $t1
-; LA32-NEXT: maskeqz $a4, $a4, $t1
-; LA32-NEXT: or $a4, $a4, $t0
-; LA32-NEXT: masknez $a7, $a7, $t1
-; LA32-NEXT: maskeqz $a3, $a3, $t1
-; LA32-NEXT: or $a3, $a3, $a7
-; LA32-NEXT: masknez $a6, $a6, $t1
-; LA32-NEXT: maskeqz $a1, $a1, $t1
-; LA32-NEXT: or $a1, $a1, $a6
-; LA32-NEXT: masknez $a2, $a2, $t1
-; LA32-NEXT: maskeqz $a5, $a5, $t1
-; LA32-NEXT: or $a2, $a5, $a2
-; LA32-NEXT: st.w $a2, $a0, 8
-; LA32-NEXT: st.w $a1, $a0, 12
-; LA32-NEXT: st.w $a3, $a0, 0
-; LA32-NEXT: st.w $a4, $a0, 4
+; LA32-NEXT: maskeqz $a4, $t1, $a4
+; LA32-NEXT: or $a3, $a4, $a3
+; LA32-NEXT: masknez $a4, $a5, $a3
+; LA32-NEXT: maskeqz $a5, $t0, $a3
+; LA32-NEXT: or $a4, $a5, $a4
+; LA32-NEXT: masknez $a5, $t3, $a3
+; LA32-NEXT: maskeqz $t0, $t4, $a3
+; LA32-NEXT: or $a5, $t0, $a5
+; LA32-NEXT: vinsgr2vr.w $vr0, $a5, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 1
+; LA32-NEXT: masknez $a4, $a6, $a3
+; LA32-NEXT: maskeqz $a5, $a7, $a3
+; LA32-NEXT: or $a4, $a5, $a4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 2
+; LA32-NEXT: masknez $a1, $a1, $a3
+; LA32-NEXT: maskeqz $a2, $a2, $a3
+; LA32-NEXT: or $a1, $a2, $a1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 3
+; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v1i128:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 8
-; LA64-NEXT: ld.d $a4, $a2, 8
-; LA64-NEXT: ld.d $a1, $a1, 0
-; LA64-NEXT: ld.d $a2, $a2, 0
-; LA64-NEXT: sltu $a5, $a3, $a4
-; LA64-NEXT: xor $a6, $a3, $a4
-; LA64-NEXT: sltui $a6, $a6, 1
-; LA64-NEXT: masknez $a5, $a5, $a6
-; LA64-NEXT: sltu $a7, $a1, $a2
-; LA64-NEXT: maskeqz $a6, $a7, $a6
-; LA64-NEXT: or $a5, $a6, $a5
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: maskeqz $a3, $a3, $a5
-; LA64-NEXT: or $a3, $a3, $a4
-; LA64-NEXT: masknez $a2, $a2, $a5
-; LA64-NEXT: maskeqz $a1, $a1, $a5
-; LA64-NEXT: or $a1, $a1, $a2
-; LA64-NEXT: st.d $a1, $a0, 0
-; LA64-NEXT: st.d $a3, $a0, 8
+; LA64-NEXT: vld $vr0, $a2, 0
+; LA64-NEXT: vld $vr1, $a1, 0
+; LA64-NEXT: vpickve2gr.d $a1, $vr0, 1
+; LA64-NEXT: vpickve2gr.d $a2, $vr1, 1
+; LA64-NEXT: sltu $a3, $a2, $a1
+; LA64-NEXT: xor $a4, $a2, $a1
+; LA64-NEXT: sltui $a4, $a4, 1
+; LA64-NEXT: masknez $a3, $a3, $a4
+; LA64-NEXT: vpickve2gr.d $a5, $vr0, 0
+; LA64-NEXT: vpickve2gr.d $a6, $vr1, 0
+; LA64-NEXT: sltu $a7, $a6, $a5
+; LA64-NEXT: maskeqz $a4, $a7, $a4
+; LA64-NEXT: or $a3, $a4, $a3
+; LA64-NEXT: masknez $a1, $a1, $a3
+; LA64-NEXT: maskeqz $a2, $a2, $a3
+; LA64-NEXT: or $a1, $a2, $a1
+; LA64-NEXT: masknez $a2, $a5, $a3
+; LA64-NEXT: maskeqz $a3, $a6, $a3
+; LA64-NEXT: or $a2, $a3, $a2
+; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1
+; LA64-NEXT: vst $vr0, $a0, 0
; LA64-NEXT: ret
entry:
%v0 = load <1 x i128>, ptr %a0
@@ -130,116 +118,86 @@ entry:
define void @select_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
; LA32-LABEL: select_v2i128:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: addi.w $sp, $sp, -16
-; LA32-NEXT: st.w $fp, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s0, $sp, 8 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s1, $sp, 4 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s2, $sp, 0 # 4-byte Folded Spill
-; LA32-NEXT: ld.w $a3, $a1, 0
-; LA32-NEXT: ld.w $a4, $a1, 8
-; LA32-NEXT: ld.w $a5, $a1, 4
-; LA32-NEXT: ld.w $a6, $a1, 12
-; LA32-NEXT: ld.w $a7, $a1, 16
-; LA32-NEXT: ld.w $t0, $a1, 24
-; LA32-NEXT: ld.w $t1, $a1, 20
-; LA32-NEXT: ld.w $a1, $a1, 28
-; LA32-NEXT: ld.w $t2, $a2, 0
-; LA32-NEXT: ld.w $t3, $a2, 8
-; LA32-NEXT: ld.w $t4, $a2, 4
-; LA32-NEXT: ld.w $t5, $a2, 12
-; LA32-NEXT: ld.w $t6, $a2, 28
-; LA32-NEXT: ld.w $t7, $a2, 20
-; LA32-NEXT: ld.w $t8, $a2, 16
-; LA32-NEXT: ld.w $a2, $a2, 24
-; LA32-NEXT: xor $fp, $a1, $t6
-; LA32-NEXT: xor $s0, $t1, $t7
-; LA32-NEXT: or $fp, $s0, $fp
-; LA32-NEXT: xor $s0, $t0, $a2
-; LA32-NEXT: xor $s1, $a7, $t8
-; LA32-NEXT: or $s0, $s1, $s0
-; LA32-NEXT: or $fp, $s0, $fp
-; LA32-NEXT: sltui $fp, $fp, 1
-; LA32-NEXT: xor $s0, $a6, $t5
-; LA32-NEXT: xor $s1, $a5, $t4
-; LA32-NEXT: or $s0, $s1, $s0
-; LA32-NEXT: xor $s1, $a4, $t3
-; LA32-NEXT: xor $s2, $a3, $t2
-; LA32-NEXT: or $s1, $s2, $s1
-; LA32-NEXT: or $s0, $s1, $s0
-; LA32-NEXT: sltui $s0, $s0, 1
-; LA32-NEXT: masknez $t4, $t4, $s0
-; LA32-NEXT: maskeqz $a5, $a5, $s0
-; LA32-NEXT: or $a5, $a5, $t4
-; LA32-NEXT: masknez $t2, $t2, $s0
-; LA32-NEXT: maskeqz $a3, $a3, $s0
-; LA32-NEXT: or $a3, $a3, $t2
-; LA32-NEXT: masknez $t2, $t5, $s0
-; LA32-NEXT: maskeqz $a6, $a6, $s0
-; LA32-NEXT: or $a6, $a6, $t2
-; LA32-NEXT: masknez $t2, $t3, $s0
-; LA32-NEXT: maskeqz $a4, $a4, $s0
-; LA32-NEXT: or $a4, $a4, $t2
-; LA32-NEXT: masknez $t2, $t7, $fp
-; LA32-NEXT: maskeqz $t1, $t1, $fp
-; LA32-NEXT: or $t1, $t1, $t2
-; LA32-NEXT: masknez $t2, $t8, $fp
-; LA32-NEXT: maskeqz $a7, $a7, $fp
-; LA32-NEXT: or $a7, $a7, $t2
-; LA32-NEXT: masknez $t2, $t6, $fp
-; LA32-NEXT: maskeqz $a1, $a1, $fp
-; LA32-NEXT: or $a1, $a1, $t2
-; LA32-NEXT: masknez $a2, $a2, $fp
-; LA32-NEXT: maskeqz $t0, $t0, $fp
-; LA32-NEXT: or $a2, $t0, $a2
-; LA32-NEXT: st.w $a2, $a0, 24
-; LA32-NEXT: st.w $a1, $a0, 28
-; LA32-NEXT: st.w $a7, $a0, 16
-; LA32-NEXT: st.w $t1, $a0, 20
-; LA32-NEXT: st.w $a4, $a0, 8
-; LA32-NEXT: st.w $a6, $a0, 12
-; LA32-NEXT: st.w $a3, $a0, 0
-; LA32-NEXT: st.w $a5, $a0, 4
-; LA32-NEXT: ld.w $s2, $sp, 0 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s1, $sp, 4 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s0, $sp, 8 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $fp, $sp, 12 # 4-byte Folded Reload
-; LA32-NEXT: addi.w $sp, $sp, 16
+; LA32-NEXT: xvld $xr0, $a2, 0
+; LA32-NEXT: xvld $xr1, $a1, 0
+; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 7
+; LA32-NEXT: xvpickve2gr.w $a2, $xr1, 7
+; LA32-NEXT: xor $a1, $a2, $a1
+; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 5
+; LA32-NEXT: xvpickve2gr.w $a3, $xr1, 5
+; LA32-NEXT: xor $a2, $a3, $a2
+; LA32-NEXT: or $a1, $a2, $a1
+; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 6
+; LA32-NEXT: xvpickve2gr.w $a3, $xr1, 6
+; LA32-NEXT: xor $a2, $a3, $a2
+; LA32-NEXT: xvpickve2gr.w $a3, $xr0, 4
+; LA32-NEXT: xvpickve2gr.w $a4, $xr1, 4
+; LA32-NEXT: xor $a3, $a4, $a3
+; LA32-NEXT: or $a2, $a3, $a2
+; LA32-NEXT: or $a1, $a2, $a1
+; LA32-NEXT: sltui $a1, $a1, 1
+; LA32-NEXT: addi.w $a2, $zero, -1
+; LA32-NEXT: maskeqz $a1, $a2, $a1
+; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 1
+; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 3
+; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 3
+; LA32-NEXT: xvpickve2gr.w $a3, $xr1, 3
+; LA32-NEXT: xor $a1, $a3, $a1
+; LA32-NEXT: xvpickve2gr.w $a3, $xr0, 1
+; LA32-NEXT: xvpickve2gr.w $a4, $xr1, 1
+; LA32-NEXT: xor $a3, $a4, $a3
+; LA32-NEXT: or $a1, $a3, $a1
+; LA32-NEXT: xvpickve2gr.w $a3, $xr0, 2
+; LA32-NEXT: xvpickve2gr.w $a4, $xr1, 2
+; LA32-NEXT: xor $a3, $a4, $a3
+; LA32-NEXT: xvpickve2gr.w $a4, $xr0, 0
+; LA32-NEXT: xvpickve2gr.w $a5, $xr1, 0
+; LA32-NEXT: xor $a4, $a5, $a4
+; LA32-NEXT: or $a3, $a4, $a3
+; LA32-NEXT: or $a1, $a3, $a1
+; LA32-NEXT: sltui $a1, $a1, 1
+; LA32-NEXT: maskeqz $a1, $a2, $a1
+; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 1
+; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 3
+; LA32-NEXT: xvpermi.q $xr3, $xr2, 2
+; LA32-NEXT: xvbitsel.v $xr0, $xr0, $xr1, $xr3
+; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v2i128:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 0
-; LA64-NEXT: ld.d $a4, $a1, 8
-; LA64-NEXT: ld.d $a5, $a1, 16
-; LA64-NEXT: ld.d $a1, $a1, 24
-; LA64-NEXT: ld.d $a6, $a2, 24
-; LA64-NEXT: ld.d $a7, $a2, 16
-; LA64-NEXT: ld.d $t0, $a2, 0
-; LA64-NEXT: ld.d $a2, $a2, 8
-; LA64-NEXT: xor $t1, $a1, $a6
-; LA64-NEXT: xor $t2, $a5, $a7
-; LA64-NEXT: or $t1, $t2, $t1
-; LA64-NEXT: sltui $t1, $t1, 1
-; LA64-NEXT: xor $t2, $a4, $a2
-; LA64-NEXT: xor $t3, $a3, $t0
-; LA64-NEXT: or $t2, $t3, $t2
-; LA64-NEXT: sltui $t2, $t2, 1
-; LA64-NEXT: masknez $a2, $a2, $t2
-; LA64-NEXT: maskeqz $a4, $a4, $t2
-; LA64-NEXT: or $a2, $a4, $a2
-; LA64-NEXT: masknez $a4, $t0, $t2
-; LA64-NEXT: maskeqz $a3, $a3, $t2
-; LA64-NEXT: or $a3, $a3, $a4
-; LA64-NEXT: masknez $a4, $a6, $t1
-; LA64-NEXT: maskeqz $a1, $a1, $t1
-; LA64-NEXT: or $a1, $a1, $a4
-; LA64-NEXT: masknez $a4, $a7, $t1
-; LA64-NEXT: maskeqz $a5, $a5, $t1
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: st.d $a4, $a0, 16
-; LA64-NEXT: st.d $a1, $a0, 24
-; LA64-NEXT: st.d $a3, $a0, 0
-; LA64-NEXT: st.d $a2, $a0, 8
+; LA64-NEXT: xvld $xr0, $a2, 0
+; LA64-NEXT: xvld $xr1, $a1, 0
+; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 3
+; LA64-NEXT: xvpickve2gr.d $a2, $xr1, 3
+; LA64-NEXT: xor $a1, $a2, $a1
+; LA64-NEXT: xvpickve2gr.d $a2, $xr0, 2
+; LA64-NEXT: xvpickve2gr.d $a3, $xr1, 2
+; LA64-NEXT: xor $a2, $a3, $a2
+; LA64-NEXT: or $a1, $a2, $a1
+; LA64-NEXT: sltui $a1, $a1, 1
+; LA64-NEXT: addi.w $a2, $zero, -1
+; LA64-NEXT: maskeqz $a1, $a2, $a1
+; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 0
+; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 1
+; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 1
+; LA64-NEXT: xvpickve2gr.d $a3, $xr1, 1
+; LA64-NEXT: xor $a1, $a3, $a1
+; LA64-NEXT: xvpickve2gr.d $a3, $xr0, 0
+; LA64-NEXT: xvpickve2gr.d $a4, $xr1, 0
+; LA64-NEXT: xor $a3, $a4, $a3
+; LA64-NEXT: or $a1, $a3, $a1
+; LA64-NEXT: sltui $a1, $a1, 1
+; LA64-NEXT: maskeqz $a1, $a2, $a1
+; LA64-NEXT: vinsgr2vr.d $vr3, $a1, 0
+; LA64-NEXT: vinsgr2vr.d $vr3, $a1, 1
+; LA64-NEXT: xvpermi.q $xr3, $xr2, 2
+; LA64-NEXT: xvbitsel.v $xr0, $xr0, $xr1, $xr3
+; LA64-NEXT: xvst $xr0, $a0, 0
; LA64-NEXT: ret
entry:
%v0 = load <2 x i128>, ptr %a0
@@ -251,23 +209,17 @@ entry:
}
define void @shuffle_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
-; LA32-LABEL: shuffle_v2i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vld $vr1, $a2, 0
-; LA32-NEXT: vst $vr0, $a0, 16
-; LA32-NEXT: vst $vr1, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: shuffle_v2i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: ld.d $a1, $a2, 0
-; LA64-NEXT: ld.d $a2, $a2, 8
-; LA64-NEXT: vst $vr0, $a0, 16
-; LA64-NEXT: st.d $a1, $a0, 0
-; LA64-NEXT: st.d $a2, $a0, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: shuffle_v2i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvld $xr1, $a2, 0
+; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 68
+; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
+; CHECK-NEXT: xvst $xr2, $a0, 0
+; CHECK-NEXT: ret
entry:
%v0 = load <2 x i128>, ptr %a0
%v1 = load <2 x i128>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/xvexth.ll b/llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
index e8d0cd4e2a2977..9595166b7d2b1b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @xvexth_h_b(ptr %a, ptr %r) nounwind {
; CHECK-LABEL: xvexth_h_b:
@@ -101,37 +101,12 @@ entry:
}
define void @xvexth_q_d(ptr %a, ptr %r) nounwind {
-; LA32-LABEL: xvexth_q_d:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: xvld $xr0, $a0, 0
-; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 2
-; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 6
-; LA32-NEXT: xvpickve2gr.w $a3, $xr0, 7
-; LA32-NEXT: xvpickve2gr.w $a4, $xr0, 3
-; LA32-NEXT: srai.w $a5, $a4, 31
-; LA32-NEXT: srai.w $a6, $a3, 31
-; LA32-NEXT: st.w $a3, $a1, 20
-; LA32-NEXT: st.w $a2, $a1, 16
-; LA32-NEXT: st.w $a4, $a1, 4
-; LA32-NEXT: st.w $a0, $a1, 0
-; LA32-NEXT: st.w $a6, $a1, 28
-; LA32-NEXT: st.w $a6, $a1, 24
-; LA32-NEXT: st.w $a5, $a1, 12
-; LA32-NEXT: st.w $a5, $a1, 8
-; LA32-NEXT: ret
-;
-; LA64-LABEL: xvexth_q_d:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: xvld $xr0, $a0, 0
-; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 3
-; LA64-NEXT: xvpickve2gr.d $a2, $xr0, 1
-; LA64-NEXT: srai.d $a2, $a2, 63
-; LA64-NEXT: srai.d $a0, $a0, 63
-; LA64-NEXT: xvstelm.d $xr0, $a1, 16, 3
-; LA64-NEXT: xvstelm.d $xr0, $a1, 0, 1
-; LA64-NEXT: st.d $a0, $a1, 24
-; LA64-NEXT: st.d $a2, $a1, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: xvexth_q_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a0, 0
+; CHECK-NEXT: xvexth.q.d $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %a
%1 = shufflevector <4 x i64> %0, <4 x i64> poison,
@@ -224,31 +199,12 @@ entry:
}
define void @xvexth_qu_du(ptr %a, ptr %r) nounwind {
-; LA32-LABEL: xvexth_qu_du:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: xvld $xr0, $a0, 0
-; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 2
-; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 3
-; LA32-NEXT: xvpickve2gr.w $a3, $xr0, 6
-; LA32-NEXT: xvpickve2gr.w $a4, $xr0, 7
-; LA32-NEXT: st.w $zero, $a1, 28
-; LA32-NEXT: st.w $zero, $a1, 24
-; LA32-NEXT: st.w $zero, $a1, 12
-; LA32-NEXT: st.w $zero, $a1, 8
-; LA32-NEXT: st.w $a4, $a1, 20
-; LA32-NEXT: st.w $a3, $a1, 16
-; LA32-NEXT: st.w $a2, $a1, 4
-; LA32-NEXT: st.w $a0, $a1, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: xvexth_qu_du:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: xvld $xr0, $a0, 0
-; LA64-NEXT: st.d $zero, $a1, 24
-; LA64-NEXT: xvstelm.d $xr0, $a1, 16, 3
-; LA64-NEXT: st.d $zero, $a1, 8
-; LA64-NEXT: xvstelm.d $xr0, $a1, 0, 1
-; LA64-NEXT: ret
+; CHECK-LABEL: xvexth_qu_du:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a0, 0
+; CHECK-NEXT: xvexth.qu.du $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a1, 0
+; CHECK-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %a
%1 = shufflevector <4 x i64> %0, <4 x i64> poison,
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
index cf8e16372088ec..6d26f2dd2b61c9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @add_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: add_v16i8:
@@ -67,52 +67,13 @@ entry:
}
define void @add_v1i128(ptr %res, ptr %a0, ptr %a1) nounwind {
-; LA32-LABEL: add_v1i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a3, $a1, 12
-; LA32-NEXT: ld.w $a4, $a1, 8
-; LA32-NEXT: ld.w $a5, $a1, 0
-; LA32-NEXT: ld.w $a1, $a1, 4
-; LA32-NEXT: ld.w $a6, $a2, 4
-; LA32-NEXT: ld.w $a7, $a2, 0
-; LA32-NEXT: ld.w $t0, $a2, 12
-; LA32-NEXT: ld.w $a2, $a2, 8
-; LA32-NEXT: add.w $a6, $a1, $a6
-; LA32-NEXT: add.w $a7, $a5, $a7
-; LA32-NEXT: sltu $a5, $a7, $a5
-; LA32-NEXT: add.w $a6, $a6, $a5
-; LA32-NEXT: sltu $t1, $a6, $a1
-; LA32-NEXT: xor $a1, $a6, $a1
-; LA32-NEXT: sltui $a1, $a1, 1
-; LA32-NEXT: masknez $t1, $t1, $a1
-; LA32-NEXT: maskeqz $a1, $a5, $a1
-; LA32-NEXT: or $a1, $a1, $t1
-; LA32-NEXT: add.w $a2, $a4, $a2
-; LA32-NEXT: add.w $a1, $a2, $a1
-; LA32-NEXT: sltu $a5, $a1, $a2
-; LA32-NEXT: add.w $a3, $a3, $t0
-; LA32-NEXT: sltu $a2, $a2, $a4
-; LA32-NEXT: add.w $a2, $a3, $a2
-; LA32-NEXT: add.w $a2, $a2, $a5
-; LA32-NEXT: st.w $a7, $a0, 0
-; LA32-NEXT: st.w $a6, $a0, 4
-; LA32-NEXT: st.w $a1, $a0, 8
-; LA32-NEXT: st.w $a2, $a0, 12
-; LA32-NEXT: ret
-;
-; LA64-LABEL: add_v1i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 0
-; LA64-NEXT: ld.d $a1, $a1, 8
-; LA64-NEXT: ld.d $a4, $a2, 8
-; LA64-NEXT: ld.d $a2, $a2, 0
-; LA64-NEXT: add.d $a1, $a1, $a4
-; LA64-NEXT: add.d $a2, $a3, $a2
-; LA64-NEXT: sltu $a3, $a2, $a3
-; LA64-NEXT: add.d $a1, $a1, $a3
-; LA64-NEXT: st.d $a2, $a0, 0
-; LA64-NEXT: st.d $a1, $a0, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: add_v1i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vadd.q $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v0 = load <1 x i128>, ptr %a0
%v1 = load <1 x i128>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
index 315349b69d8d6a..b6784a26572df7 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @sub_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: sub_v16i8:
@@ -67,52 +67,13 @@ entry:
}
define void @sub_v1i128(ptr %res, ptr %a0, ptr %a1) nounwind {
-; LA32-LABEL: sub_v1i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a3, $a1, 12
-; LA32-NEXT: ld.w $a4, $a1, 8
-; LA32-NEXT: ld.w $a5, $a1, 0
-; LA32-NEXT: ld.w $a1, $a1, 4
-; LA32-NEXT: ld.w $a6, $a2, 4
-; LA32-NEXT: ld.w $a7, $a2, 12
-; LA32-NEXT: ld.w $t0, $a2, 8
-; LA32-NEXT: ld.w $a2, $a2, 0
-; LA32-NEXT: sltu $t1, $a1, $a6
-; LA32-NEXT: xor $t2, $a1, $a6
-; LA32-NEXT: sltui $t2, $t2, 1
-; LA32-NEXT: masknez $t1, $t1, $t2
-; LA32-NEXT: sltu $t3, $a5, $a2
-; LA32-NEXT: maskeqz $t2, $t3, $t2
-; LA32-NEXT: or $t1, $t2, $t1
-; LA32-NEXT: sub.w $t2, $a4, $t0
-; LA32-NEXT: sltu $t4, $t2, $t1
-; LA32-NEXT: sltu $a4, $a4, $t0
-; LA32-NEXT: sub.w $a3, $a3, $a7
-; LA32-NEXT: sub.w $a3, $a3, $a4
-; LA32-NEXT: sub.w $a3, $a3, $t4
-; LA32-NEXT: sub.w $a4, $t2, $t1
-; LA32-NEXT: sub.w $a1, $a1, $a6
-; LA32-NEXT: sub.w $a1, $a1, $t3
-; LA32-NEXT: sub.w $a2, $a5, $a2
-; LA32-NEXT: st.w $a2, $a0, 0
-; LA32-NEXT: st.w $a1, $a0, 4
-; LA32-NEXT: st.w $a4, $a0, 8
-; LA32-NEXT: st.w $a3, $a0, 12
-; LA32-NEXT: ret
-;
-; LA64-LABEL: sub_v1i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 8
-; LA64-NEXT: ld.d $a1, $a1, 0
-; LA64-NEXT: ld.d $a4, $a2, 0
-; LA64-NEXT: ld.d $a2, $a2, 8
-; LA64-NEXT: sltu $a5, $a1, $a4
-; LA64-NEXT: sub.d $a2, $a3, $a2
-; LA64-NEXT: sub.d $a2, $a2, $a5
-; LA64-NEXT: sub.d $a1, $a1, $a4
-; LA64-NEXT: st.d $a1, $a0, 0
-; LA64-NEXT: st.d $a2, $a0, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: sub_v1i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a2, 0
+; CHECK-NEXT: vsub.q $vr0, $vr0, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v0 = load <1 x i128>, ptr %a0
%v1 = load <1 x i128>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-i128.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-i128.ll
index b4eedb9213dea9..d24a6da4b7a3c1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-i128.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-i128.ll
@@ -18,29 +18,13 @@ entry:
}
define void @load_store_v2i128(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: load_store_v2i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: ld.w $a2, $a1, 24
-; LA32-NEXT: ld.w $a3, $a1, 28
-; LA32-NEXT: ld.w $a4, $a1, 16
-; LA32-NEXT: ld.w $a1, $a1, 20
-; LA32-NEXT: st.w $a2, $a0, 24
-; LA32-NEXT: st.w $a3, $a0, 28
-; LA32-NEXT: st.w $a4, $a0, 16
-; LA32-NEXT: st.w $a1, $a0, 20
-; LA32-NEXT: vst $vr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: load_store_v2i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a2, $a1, 16
-; LA64-NEXT: ld.d $a3, $a1, 24
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: st.d $a2, $a0, 16
-; LA64-NEXT: st.d $a3, $a0, 24
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: load_store_v2i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a1, 16
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: vst $vr1, $a0, 16
+; CHECK-NEXT: ret
entry:
%v = load <2 x i128>, ptr %a
store <2 x i128> %v, ptr %res
@@ -50,73 +34,79 @@ entry:
define void @select_v1i128(ptr %res, ptr %a0, ptr %a1) nounwind {
; LA32-LABEL: select_v1i128:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a3, $a1, 0
-; LA32-NEXT: ld.w $a4, $a1, 4
-; LA32-NEXT: ld.w $a5, $a1, 8
-; LA32-NEXT: ld.w $a1, $a1, 12
-; LA32-NEXT: ld.w $a6, $a2, 12
-; LA32-NEXT: ld.w $a7, $a2, 0
-; LA32-NEXT: ld.w $t0, $a2, 4
-; LA32-NEXT: ld.w $a2, $a2, 8
-; LA32-NEXT: sltu $t1, $a1, $a6
-; LA32-NEXT: xor $t2, $a1, $a6
-; LA32-NEXT: sltui $t3, $t2, 1
-; LA32-NEXT: masknez $t1, $t1, $t3
-; LA32-NEXT: sltu $t4, $a5, $a2
-; LA32-NEXT: maskeqz $t3, $t4, $t3
-; LA32-NEXT: or $t1, $t3, $t1
-; LA32-NEXT: xor $t3, $a5, $a2
-; LA32-NEXT: or $t2, $t3, $t2
+; LA32-NEXT: vld $vr0, $a2, 0
+; LA32-NEXT: vld $vr1, $a1, 0
+; LA32-NEXT: vpickve2gr.w $a1, $vr0, 3
+; LA32-NEXT: vpickve2gr.w $a2, $vr1, 3
+; LA32-NEXT: sltu $a3, $a2, $a1
+; LA32-NEXT: xor $a4, $a2, $a1
+; LA32-NEXT: sltui $a5, $a4, 1
+; LA32-NEXT: masknez $a3, $a3, $a5
+; LA32-NEXT: vpickve2gr.w $a6, $vr0, 2
+; LA32-NEXT: vpickve2gr.w $a7, $vr1, 2
+; LA32-NEXT: sltu $t0, $a7, $a6
+; LA32-NEXT: maskeqz $a5, $t0, $a5
+; LA32-NEXT: or $a3, $a5, $a3
+; LA32-NEXT: xor $a5, $a7, $a6
+; LA32-NEXT: or $a4, $a5, $a4
+; LA32-NEXT: sltui $a4, $a4, 1
+; LA32-NEXT: masknez $a3, $a3, $a4
+; LA32-NEXT: vpickve2gr.w $a5, $vr0, 1
+; LA32-NEXT: vpickve2gr.w $t0, $vr1, 1
+; LA32-NEXT: sltu $t1, $t0, $a5
+; LA32-NEXT: xor $t2, $t0, $a5
; LA32-NEXT: sltui $t2, $t2, 1
; LA32-NEXT: masknez $t1, $t1, $t2
-; LA32-NEXT: sltu $t3, $a4, $t0
-; LA32-NEXT: xor $t4, $a4, $t0
-; LA32-NEXT: sltui $t4, $t4, 1
-; LA32-NEXT: masknez $t3, $t3, $t4
-; LA32-NEXT: sltu $t5, $a3, $a7
-; LA32-NEXT: maskeqz $t4, $t5, $t4
-; LA32-NEXT: or $t3, $t4, $t3
-; LA32-NEXT: maskeqz $t2, $t3, $t2
+; LA32-NEXT: vpickve2gr.w $t3, $vr0, 0
+; LA32-NEXT: vpickve2gr.w $t4, $vr1, 0
+; LA32-NEXT: sltu $t5, $t4, $t3
+; LA32-NEXT: maskeqz $t2, $t5, $t2
; LA32-NEXT: or $t1, $t2, $t1
-; LA32-NEXT: masknez $t0, $t0, $t1
-; LA32-NEXT: maskeqz $a4, $a4, $t1
-; LA32-NEXT: or $a4, $a4, $t0
-; LA32-NEXT: masknez $a7, $a7, $t1
-; LA32-NEXT: maskeqz $a3, $a3, $t1
-; LA32-NEXT: or $a3, $a3, $a7
-; LA32-NEXT: masknez $a6, $a6, $t1
-; LA32-NEXT: maskeqz $a1, $a1, $t1
-; LA32-NEXT: or $a1, $a1, $a6
-; LA32-NEXT: masknez $a2, $a2, $t1
-; LA32-NEXT: maskeqz $a5, $a5, $t1
-; LA32-NEXT: or $a2, $a5, $a2
-; LA32-NEXT: st.w $a2, $a0, 8
-; LA32-NEXT: st.w $a1, $a0, 12
-; LA32-NEXT: st.w $a3, $a0, 0
-; LA32-NEXT: st.w $a4, $a0, 4
+; LA32-NEXT: maskeqz $a4, $t1, $a4
+; LA32-NEXT: or $a3, $a4, $a3
+; LA32-NEXT: masknez $a4, $a5, $a3
+; LA32-NEXT: maskeqz $a5, $t0, $a3
+; LA32-NEXT: or $a4, $a5, $a4
+; LA32-NEXT: masknez $a5, $t3, $a3
+; LA32-NEXT: maskeqz $t0, $t4, $a3
+; LA32-NEXT: or $a5, $t0, $a5
+; LA32-NEXT: vinsgr2vr.w $vr0, $a5, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 1
+; LA32-NEXT: masknez $a4, $a6, $a3
+; LA32-NEXT: maskeqz $a5, $a7, $a3
+; LA32-NEXT: or $a4, $a5, $a4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 2
+; LA32-NEXT: masknez $a1, $a1, $a3
+; LA32-NEXT: maskeqz $a2, $a2, $a3
+; LA32-NEXT: or $a1, $a2, $a1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 3
+; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v1i128:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 8
-; LA64-NEXT: ld.d $a4, $a2, 8
-; LA64-NEXT: ld.d $a1, $a1, 0
-; LA64-NEXT: ld.d $a2, $a2, 0
-; LA64-NEXT: sltu $a5, $a3, $a4
-; LA64-NEXT: xor $a6, $a3, $a4
-; LA64-NEXT: sltui $a6, $a6, 1
-; LA64-NEXT: masknez $a5, $a5, $a6
-; LA64-NEXT: sltu $a7, $a1, $a2
-; LA64-NEXT: maskeqz $a6, $a7, $a6
-; LA64-NEXT: or $a5, $a6, $a5
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: maskeqz $a3, $a3, $a5
-; LA64-NEXT: or $a3, $a3, $a4
-; LA64-NEXT: masknez $a2, $a2, $a5
-; LA64-NEXT: maskeqz $a1, $a1, $a5
-; LA64-NEXT: or $a1, $a1, $a2
-; LA64-NEXT: st.d $a1, $a0, 0
-; LA64-NEXT: st.d $a3, $a0, 8
+; LA64-NEXT: vld $vr0, $a2, 0
+; LA64-NEXT: vld $vr1, $a1, 0
+; LA64-NEXT: vpickve2gr.d $a1, $vr0, 1
+; LA64-NEXT: vpickve2gr.d $a2, $vr1, 1
+; LA64-NEXT: sltu $a3, $a2, $a1
+; LA64-NEXT: xor $a4, $a2, $a1
+; LA64-NEXT: sltui $a4, $a4, 1
+; LA64-NEXT: masknez $a3, $a3, $a4
+; LA64-NEXT: vpickve2gr.d $a5, $vr0, 0
+; LA64-NEXT: vpickve2gr.d $a6, $vr1, 0
+; LA64-NEXT: sltu $a7, $a6, $a5
+; LA64-NEXT: maskeqz $a4, $a7, $a4
+; LA64-NEXT: or $a3, $a4, $a3
+; LA64-NEXT: masknez $a1, $a1, $a3
+; LA64-NEXT: maskeqz $a2, $a2, $a3
+; LA64-NEXT: or $a1, $a2, $a1
+; LA64-NEXT: masknez $a2, $a5, $a3
+; LA64-NEXT: maskeqz $a3, $a6, $a3
+; LA64-NEXT: or $a2, $a3, $a2
+; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1
+; LA64-NEXT: vst $vr0, $a0, 0
; LA64-NEXT: ret
entry:
%v0 = load <1 x i128>, ptr %a0
@@ -135,70 +125,76 @@ define void @select_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
; LA32-NEXT: st.w $s0, $sp, 8 # 4-byte Folded Spill
; LA32-NEXT: st.w $s1, $sp, 4 # 4-byte Folded Spill
; LA32-NEXT: st.w $s2, $sp, 0 # 4-byte Folded Spill
-; LA32-NEXT: ld.w $a3, $a1, 0
-; LA32-NEXT: ld.w $a4, $a1, 8
-; LA32-NEXT: ld.w $a5, $a1, 4
-; LA32-NEXT: ld.w $a6, $a1, 12
-; LA32-NEXT: ld.w $a7, $a1, 16
-; LA32-NEXT: ld.w $t0, $a1, 24
-; LA32-NEXT: ld.w $t1, $a1, 20
-; LA32-NEXT: ld.w $a1, $a1, 28
-; LA32-NEXT: ld.w $t2, $a2, 0
-; LA32-NEXT: ld.w $t3, $a2, 8
-; LA32-NEXT: ld.w $t4, $a2, 4
-; LA32-NEXT: ld.w $t5, $a2, 12
-; LA32-NEXT: ld.w $t6, $a2, 28
-; LA32-NEXT: ld.w $t7, $a2, 20
-; LA32-NEXT: ld.w $t8, $a2, 16
-; LA32-NEXT: ld.w $a2, $a2, 24
-; LA32-NEXT: xor $fp, $a1, $t6
-; LA32-NEXT: xor $s0, $t1, $t7
-; LA32-NEXT: or $fp, $s0, $fp
-; LA32-NEXT: xor $s0, $t0, $a2
-; LA32-NEXT: xor $s1, $a7, $t8
-; LA32-NEXT: or $s0, $s1, $s0
-; LA32-NEXT: or $fp, $s0, $fp
-; LA32-NEXT: sltui $fp, $fp, 1
-; LA32-NEXT: xor $s0, $a6, $t5
-; LA32-NEXT: xor $s1, $a5, $t4
-; LA32-NEXT: or $s0, $s1, $s0
-; LA32-NEXT: xor $s1, $a4, $t3
-; LA32-NEXT: xor $s2, $a3, $t2
-; LA32-NEXT: or $s1, $s2, $s1
-; LA32-NEXT: or $s0, $s1, $s0
-; LA32-NEXT: sltui $s0, $s0, 1
-; LA32-NEXT: masknez $t4, $t4, $s0
-; LA32-NEXT: maskeqz $a5, $a5, $s0
-; LA32-NEXT: or $a5, $a5, $t4
-; LA32-NEXT: masknez $t2, $t2, $s0
-; LA32-NEXT: maskeqz $a3, $a3, $s0
-; LA32-NEXT: or $a3, $a3, $t2
-; LA32-NEXT: masknez $t2, $t5, $s0
-; LA32-NEXT: maskeqz $a6, $a6, $s0
-; LA32-NEXT: or $a6, $a6, $t2
-; LA32-NEXT: masknez $t2, $t3, $s0
-; LA32-NEXT: maskeqz $a4, $a4, $s0
-; LA32-NEXT: or $a4, $a4, $t2
-; LA32-NEXT: masknez $t2, $t7, $fp
-; LA32-NEXT: maskeqz $t1, $t1, $fp
-; LA32-NEXT: or $t1, $t1, $t2
-; LA32-NEXT: masknez $t2, $t8, $fp
-; LA32-NEXT: maskeqz $a7, $a7, $fp
-; LA32-NEXT: or $a7, $a7, $t2
-; LA32-NEXT: masknez $t2, $t6, $fp
-; LA32-NEXT: maskeqz $a1, $a1, $fp
-; LA32-NEXT: or $a1, $a1, $t2
-; LA32-NEXT: masknez $a2, $a2, $fp
-; LA32-NEXT: maskeqz $t0, $t0, $fp
-; LA32-NEXT: or $a2, $t0, $a2
-; LA32-NEXT: st.w $a2, $a0, 24
-; LA32-NEXT: st.w $a1, $a0, 28
-; LA32-NEXT: st.w $a7, $a0, 16
-; LA32-NEXT: st.w $t1, $a0, 20
-; LA32-NEXT: st.w $a4, $a0, 8
-; LA32-NEXT: st.w $a6, $a0, 12
-; LA32-NEXT: st.w $a3, $a0, 0
-; LA32-NEXT: st.w $a5, $a0, 4
+; LA32-NEXT: vld $vr0, $a2, 0
+; LA32-NEXT: vld $vr1, $a1, 0
+; LA32-NEXT: vpickve2gr.w $a3, $vr0, 3
+; LA32-NEXT: vpickve2gr.w $a4, $vr1, 3
+; LA32-NEXT: xor $a5, $a4, $a3
+; LA32-NEXT: vpickve2gr.w $a7, $vr0, 1
+; LA32-NEXT: vpickve2gr.w $t0, $vr1, 1
+; LA32-NEXT: xor $a6, $t0, $a7
+; LA32-NEXT: or $t1, $a6, $a5
+; LA32-NEXT: vpickve2gr.w $a5, $vr0, 2
+; LA32-NEXT: vpickve2gr.w $a6, $vr1, 2
+; LA32-NEXT: xor $t2, $a6, $a5
+; LA32-NEXT: vpickve2gr.w $t3, $vr0, 0
+; LA32-NEXT: vpickve2gr.w $t4, $vr1, 0
+; LA32-NEXT: xor $t5, $t4, $t3
+; LA32-NEXT: or $t2, $t5, $t2
+; LA32-NEXT: vld $vr0, $a2, 16
+; LA32-NEXT: vld $vr1, $a1, 16
+; LA32-NEXT: or $a1, $t2, $t1
+; LA32-NEXT: sltui $a1, $a1, 1
+; LA32-NEXT: vpickve2gr.w $a2, $vr0, 3
+; LA32-NEXT: vpickve2gr.w $t1, $vr1, 3
+; LA32-NEXT: xor $t2, $t1, $a2
+; LA32-NEXT: vpickve2gr.w $t5, $vr0, 1
+; LA32-NEXT: vpickve2gr.w $t6, $vr1, 1
+; LA32-NEXT: xor $t7, $t6, $t5
+; LA32-NEXT: or $t2, $t7, $t2
+; LA32-NEXT: vpickve2gr.w $t7, $vr0, 2
+; LA32-NEXT: vpickve2gr.w $t8, $vr1, 2
+; LA32-NEXT: xor $fp, $t8, $t7
+; LA32-NEXT: vpickve2gr.w $s0, $vr0, 0
+; LA32-NEXT: vpickve2gr.w $s1, $vr1, 0
+; LA32-NEXT: xor $s2, $s1, $s0
+; LA32-NEXT: or $fp, $s2, $fp
+; LA32-NEXT: or $t2, $fp, $t2
+; LA32-NEXT: sltui $t2, $t2, 1
+; LA32-NEXT: masknez $t5, $t5, $t2
+; LA32-NEXT: maskeqz $t6, $t6, $t2
+; LA32-NEXT: or $t5, $t6, $t5
+; LA32-NEXT: masknez $t6, $s0, $t2
+; LA32-NEXT: maskeqz $fp, $s1, $t2
+; LA32-NEXT: or $t6, $fp, $t6
+; LA32-NEXT: vinsgr2vr.w $vr0, $t6, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $t5, 1
+; LA32-NEXT: masknez $t5, $t7, $t2
+; LA32-NEXT: maskeqz $t6, $t8, $t2
+; LA32-NEXT: or $t5, $t6, $t5
+; LA32-NEXT: vinsgr2vr.w $vr0, $t5, 2
+; LA32-NEXT: masknez $a2, $a2, $t2
+; LA32-NEXT: maskeqz $t1, $t1, $t2
+; LA32-NEXT: or $a2, $t1, $a2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3
+; LA32-NEXT: masknez $a2, $a7, $a1
+; LA32-NEXT: maskeqz $a7, $t0, $a1
+; LA32-NEXT: or $a2, $a7, $a2
+; LA32-NEXT: masknez $a7, $t3, $a1
+; LA32-NEXT: maskeqz $t0, $t4, $a1
+; LA32-NEXT: or $a7, $t0, $a7
+; LA32-NEXT: vinsgr2vr.w $vr1, $a7, 0
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 1
+; LA32-NEXT: masknez $a2, $a5, $a1
+; LA32-NEXT: maskeqz $a5, $a6, $a1
+; LA32-NEXT: or $a2, $a5, $a2
+; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 2
+; LA32-NEXT: masknez $a2, $a3, $a1
+; LA32-NEXT: maskeqz $a1, $a4, $a1
+; LA32-NEXT: or $a1, $a1, $a2
+; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3
+; LA32-NEXT: vst $vr1, $a0, 0
+; LA32-NEXT: vst $vr0, $a0, 16
; LA32-NEXT: ld.w $s2, $sp, 0 # 4-byte Folded Reload
; LA32-NEXT: ld.w $s1, $sp, 4 # 4-byte Folded Reload
; LA32-NEXT: ld.w $s0, $sp, 8 # 4-byte Folded Reload
@@ -208,38 +204,44 @@ define void @select_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
;
; LA64-LABEL: select_v2i128:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a3, $a1, 0
-; LA64-NEXT: ld.d $a4, $a1, 8
-; LA64-NEXT: ld.d $a5, $a1, 16
-; LA64-NEXT: ld.d $a1, $a1, 24
-; LA64-NEXT: ld.d $a6, $a2, 24
-; LA64-NEXT: ld.d $a7, $a2, 16
-; LA64-NEXT: ld.d $t0, $a2, 0
-; LA64-NEXT: ld.d $a2, $a2, 8
-; LA64-NEXT: xor $t1, $a1, $a6
-; LA64-NEXT: xor $t2, $a5, $a7
-; LA64-NEXT: or $t1, $t2, $t1
-; LA64-NEXT: sltui $t1, $t1, 1
-; LA64-NEXT: xor $t2, $a4, $a2
-; LA64-NEXT: xor $t3, $a3, $t0
-; LA64-NEXT: or $t2, $t3, $t2
-; LA64-NEXT: sltui $t2, $t2, 1
-; LA64-NEXT: masknez $a2, $a2, $t2
-; LA64-NEXT: maskeqz $a4, $a4, $t2
-; LA64-NEXT: or $a2, $a4, $a2
-; LA64-NEXT: masknez $a4, $t0, $t2
-; LA64-NEXT: maskeqz $a3, $a3, $t2
-; LA64-NEXT: or $a3, $a3, $a4
-; LA64-NEXT: masknez $a4, $a6, $t1
-; LA64-NEXT: maskeqz $a1, $a1, $t1
-; LA64-NEXT: or $a1, $a1, $a4
-; LA64-NEXT: masknez $a4, $a7, $t1
-; LA64-NEXT: maskeqz $a5, $a5, $t1
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: st.d $a4, $a0, 16
-; LA64-NEXT: st.d $a1, $a0, 24
-; LA64-NEXT: st.d $a3, $a0, 0
-; LA64-NEXT: st.d $a2, $a0, 8
+; LA64-NEXT: vld $vr0, $a2, 0
+; LA64-NEXT: vld $vr1, $a1, 0
+; LA64-NEXT: vpickve2gr.d $a3, $vr0, 1
+; LA64-NEXT: vpickve2gr.d $a4, $vr1, 1
+; LA64-NEXT: xor $a5, $a4, $a3
+; LA64-NEXT: vpickve2gr.d $a6, $vr0, 0
+; LA64-NEXT: vpickve2gr.d $a7, $vr1, 0
+; LA64-NEXT: xor $t0, $a7, $a6
+; LA64-NEXT: vld $vr0, $a2, 16
+; LA64-NEXT: vld $vr1, $a1, 16
+; LA64-NEXT: or $a1, $t0, $a5
+; LA64-NEXT: sltui $a1, $a1, 1
+; LA64-NEXT: vpickve2gr.d $a2, $vr0, 1
+; LA64-NEXT: vpickve2gr.d $a5, $vr1, 1
+; LA64-NEXT: xor $t0, $a5, $a2
+; LA64-NEXT: vpickve2gr.d $t1, $vr0, 0
+; LA64-NEXT: vpickve2gr.d $t2, $vr1, 0
+; LA64-NEXT: xor $t3, $t2, $t1
+; LA64-NEXT: or $t0, $t3, $t0
+; LA64-NEXT: sltui $t0, $t0, 1
+; LA64-NEXT: masknez $a2, $a2, $t0
+; LA64-NEXT: maskeqz $a5, $a5, $t0
+; LA64-NEXT: or $a2, $a5, $a2
+; LA64-NEXT: masknez $a5, $t1, $t0
+; LA64-NEXT: maskeqz $t0, $t2, $t0
+; LA64-NEXT: or $a5, $t0, $a5
+; LA64-NEXT: vinsgr2vr.d $vr0, $a5, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 1
+; LA64-NEXT: masknez $a2, $a3, $a1
+; LA64-NEXT: maskeqz $a3, $a4, $a1
+; LA64-NEXT: or $a2, $a3, $a2
+; LA64-NEXT: masknez $a3, $a6, $a1
+; LA64-NEXT: maskeqz $a1, $a7, $a1
+; LA64-NEXT: or $a1, $a1, $a3
+; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 0
+; LA64-NEXT: vinsgr2vr.d $vr1, $a2, 1
+; LA64-NEXT: vst $vr1, $a0, 0
+; LA64-NEXT: vst $vr0, $a0, 16
; LA64-NEXT: ret
entry:
%v0 = load <2 x i128>, ptr %a0
@@ -251,23 +253,13 @@ entry:
}
define void @shuffle_v2i128(ptr %res, ptr %a0, ptr %a1) nounwind {
-; LA32-LABEL: shuffle_v2i128:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vld $vr1, $a2, 0
-; LA32-NEXT: vst $vr0, $a0, 16
-; LA32-NEXT: vst $vr1, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: shuffle_v2i128:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: ld.d $a1, $a2, 0
-; LA64-NEXT: ld.d $a2, $a2, 8
-; LA64-NEXT: vst $vr0, $a0, 16
-; LA64-NEXT: st.d $a1, $a0, 0
-; LA64-NEXT: st.d $a2, $a0, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: shuffle_v2i128:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a2, 0
+; CHECK-NEXT: vld $vr1, $a1, 0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: vst $vr1, $a0, 16
+; CHECK-NEXT: ret
entry:
%v0 = load <2 x i128>, ptr %a0
%v1 = load <2 x i128>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vexth.ll b/llvm/test/CodeGen/LoongArch/lsx/vexth.ll
index b8e87a0ccd058c..82cf5954187c57 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vexth.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vexth.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @vexth_h_b(ptr %a, ptr %r) nounwind {
; CHECK-LABEL: vexth_h_b:
@@ -95,25 +95,12 @@ entry:
}
define void @vexth_q_d(ptr %a, ptr %r) nounwind {
-; LA32-LABEL: vexth_q_d:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a0, 0
-; LA32-NEXT: vpickve2gr.w $a0, $vr0, 2
-; LA32-NEXT: vpickve2gr.w $a2, $vr0, 3
-; LA32-NEXT: srai.w $a3, $a2, 31
-; LA32-NEXT: st.w $a2, $a1, 4
-; LA32-NEXT: st.w $a0, $a1, 0
-; LA32-NEXT: st.w $a3, $a1, 12
-; LA32-NEXT: st.w $a3, $a1, 8
-; LA32-NEXT: ret
-;
-; LA64-LABEL: vexth_q_d:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 8
-; LA64-NEXT: srai.d $a2, $a0, 63
-; LA64-NEXT: st.d $a0, $a1, 0
-; LA64-NEXT: st.d $a2, $a1, 8
-; LA64-NEXT: ret
+; CHECK-LABEL: vexth_q_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vexth.q.d $vr0, $vr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
entry:
%0 = load <2 x i64>, ptr %a
%1 = shufflevector <2 x i64> %0, <2 x i64> poison, <1 x i32> <i32 1>
@@ -215,23 +202,12 @@ entry:
}
define void @vexth_qu_du(ptr %a, ptr %r) nounwind {
-; LA32-LABEL: vexth_qu_du:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a0, 0
-; LA32-NEXT: vpickve2gr.w $a0, $vr0, 2
-; LA32-NEXT: vpickve2gr.w $a2, $vr0, 3
-; LA32-NEXT: st.w $zero, $a1, 12
-; LA32-NEXT: st.w $zero, $a1, 8
-; LA32-NEXT: st.w $a2, $a1, 4
-; LA32-NEXT: st.w $a0, $a1, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: vexth_qu_du:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 8
-; LA64-NEXT: st.d $zero, $a1, 8
-; LA64-NEXT: st.d $a0, $a1, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: vexth_qu_du:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vexth.qu.du $vr0, $vr0
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
entry:
%0 = load <2 x i64>, ptr %a
%1 = shufflevector <2 x i64> %0, <2 x i64> poison, <1 x i32> <i32 1>
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