[llvm-branch-commits] [llvm] 3dcb036 - Revert "[AMDGPU] Handle gfx950 v_pk_{add, mul, fma}_f32 invalid op_sel (#231506)"
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 14 05:14:25 PDT 2026
Author: Matt Arsenault
Date: 2026-10-14T14:14:20+02:00
New Revision: 3dcb036307d0ab929615807177dbee4ae1d3d604
URL: https://github.com/llvm/llvm-project/commit/3dcb036307d0ab929615807177dbee4ae1d3d604
DIFF: https://github.com/llvm/llvm-project/commit/3dcb036307d0ab929615807177dbee4ae1d3d604.diff
LOG: Revert "[AMDGPU] Handle gfx950 v_pk_{add,mul,fma}_f32 invalid op_sel (#231506)"
This reverts commit 4f792b8a893f804dcf8f68366b429be939ecaaee.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/test/MC/AMDGPU/gfx950_err.s
Removed:
llvm/test/CodeGen/AMDGPU/gfx950-pk-f32-invalid-op-sel.ll
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 5fac581e62c924..3882b58b0a45c2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4672,22 +4672,6 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
return selectG_EXTRACT_VECTOR_ELT(I);
case TargetOpcode::G_INSERT_VECTOR_ELT:
return selectG_INSERT_VECTOR_ELT(I);
- case TargetOpcode::G_FMA: {
- if (!STI.hasPkF32InvalidOpSel())
- return selectImpl(I, *CoverageInfo);
-
- Register VReg = I.getOperand(0).getReg();
- if (!selectImpl(I, *CoverageInfo))
- return false;
-
- MachineInstr *Sel = MRI->getVRegDef(VReg);
- // Fix GFX950 v_pk_fma_f32 invalid op_sel by decomposing.
- if (Sel->getOpcode() == AMDGPU::V_PK_FMA_F32 &&
- !TII.isLegalPkFMAF32OpSel(*Sel))
- TII.decomposePkFMAF32(*Sel, *MRI);
-
- return true;
- }
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD:
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_NORET:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 0231e75eb2f476..e21510cf45bed7 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4815,22 +4815,6 @@ bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
return false;
}
- // gfx950 v_pk_add/mul/fma_f32 have several invalid op_sel encodings
- if (getFeatureBits()[AMDGPU::FeatureGFX950Insts] &&
- (Opc == AMDGPU::V_PK_ADD_F32_vi || Opc == AMDGPU::V_PK_MUL_F32_vi ||
- Opc == AMDGPU::V_PK_FMA_F32_vi)) {
- int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
- unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
-
- // op_sel[2:1] == 2'b01, 2'b10, or 2'b11 for v_pk_fma.
- if (Opc == AMDGPU::V_PK_FMA_F32_vi &&
- (((OpSel >> 1) & 1) || ((OpSel >> 2) & 1)))
- return false;
- // op_sel[1:0] == 2'b10 for v_pk_add/mul_f32.
- else if ((OpSel & 3) == 2)
- return false;
- }
-
// Packed math FP32 instructions typically accept SGPRs or VGPRs as source
// operands. On gfx12+, if a source operand uses SGPRs, the HW can only read
// the first SGPR and use it for both the low and high operations.
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 2cadb410df06e2..20982c540679cb 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1964,7 +1964,6 @@ void GCNHazardRecognizer::fixHazards(MachineInstr *MI) {
fixWMMAHazards(MI); // fall-through if co-execution is enabled.
fixWMMACoexecutionHazards(MI);
fixShift64HighRegBug(MI);
- fixPkF32InvalidOpSel(MI);
fixVALUMaskWriteHazard(MI);
fixRequiredExportPriority(MI);
if (ST.hasVPermPk16Hazard())
@@ -3072,54 +3071,6 @@ bool GCNHazardRecognizer::fixShift64HighRegBug(MachineInstr *MI) {
return true;
}
-// Handle GFX950 v_pk_{add,mul,fma}_f32 invalid op_sels
-// 1. Fix: opsel[1:0]==2’b10 : Packed ADD_F32/MUL_F32
-// 2. Fail: opsel[2:1]==2'b01/2'b10/2'b11 : Packed FMA_F32
-bool GCNHazardRecognizer::fixPkF32InvalidOpSel(MachineInstr *MI) {
- if (!ST.hasPkF32InvalidOpSel())
- return false;
-
- switch (MI->getOpcode()) {
- default:
- return false;
- case AMDGPU::V_PK_ADD_F32:
- case AMDGPU::V_PK_MUL_F32:
- case AMDGPU::V_PK_FMA_F32:
- break;
- }
-
- const MachineOperand *Src0Mods =
- TII.getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers);
- const MachineOperand *Src1Mods =
- TII.getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
- if (!Src0Mods || !Src1Mods)
- return false;
-
- if (MI->getOpcode() != AMDGPU::V_PK_FMA_F32) {
- if (!(Src0Mods->getImm() & SISrcMods::OP_SEL_0) &&
- (Src1Mods->getImm() & SISrcMods::OP_SEL_0)) {
- if (!TII.commuteInstruction(*MI)) {
- reportFatalInternalError(
- "cannot swap the GFX950 v_pk_add/mul_f32 src0 and src1: " +
- Twine(TII.getName(MI->getOpcode())));
- }
- return true;
- }
- return false;
- }
-
- // Safety net: v_pk_fma_f32 invalid opsels are expected to already
- // be prevented earlier, so just fail loudly if it is ever seen here
- // instead of silently miscompiling, as a safeguard against future changes.
- if (!TII.isLegalPkFMAF32OpSel(*MI)) {
- reportFatalInternalError("GFX950 v_pk_fma_f32 has an invalid op_sel that "
- "should have been legalized earlier in the "
- "pipeline");
- }
-
- return false;
-}
-
int GCNHazardRecognizer::checkNSAtoVMEMHazard(MachineInstr *MI) const {
int NSAtoVMEMWaitStates = 1;
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
index ca340a320f4234..c1d465a5c559ec 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
@@ -242,7 +242,6 @@ class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
const MachineInstr &MI) const;
bool fixShift64HighRegBug(MachineInstr *MI);
bool fixVPermPk16Hazard(MachineInstr *MI);
- bool fixPkF32InvalidOpSel(MachineInstr *MI);
bool fixVALUMaskWriteHazard(MachineInstr *MI);
bool fixRequiredExportPriority(MachineInstr *MI);
bool fixGetRegWaitIdle(MachineInstr *MI);
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 24f08aa790a206..fe4d5acedb0511 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -618,8 +618,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return getGeneration() == GFX11;
}
- bool hasPkF32InvalidOpSel() const { return HasGFX950Insts; }
-
bool hasCvtScaleForwardingHazard() const { return HasGFX950Insts; }
bool hasPermlaneForwardingHazard() const { return HasGFX950Insts; }
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f2db47d4de8a0f..5a834dd4235627 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6756,131 +6756,6 @@ bool SIInstrInfo::isLegalSingleSGPRReadInstOperand(
return !OpSel && !OpSelHi;
}
-// Check if V_PK_FMA_F32 does not have the invalid opsel conditions.
-bool SIInstrInfo::isLegalPkFMAF32OpSel(const MachineInstr &MI) const {
- if (!ST.hasPkF32InvalidOpSel() || MI.getOpcode() != AMDGPU::V_PK_FMA_F32)
- return true;
-
- const MachineOperand *Src1Mods =
- getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
- const MachineOperand *Src2Mods =
- getNamedOperand(MI, AMDGPU::OpName::src2_modifiers);
-
- auto HasOpSel0 = [](const MachineOperand *Mods) {
- return Mods->getImm() & SISrcMods::OP_SEL_0;
- };
-
- // Illegal iff opsel[2:1] == 2'b01, 2'b10, or 2'b11
- return !HasOpSel0(Src1Mods) && !HasOpSel0(Src2Mods);
-}
-
-void SIInstrInfo::decomposePkFMAF32(MachineInstr &MI,
- MachineRegisterInfo &MRI) const {
- assert(MI.getOpcode() == AMDGPU::V_PK_FMA_F32);
-
- MachineBasicBlock &MBB = *MI.getParent();
- const DebugLoc &DL = MI.getDebugLoc();
-
- MachineOperand *Srcs[3] = {getNamedOperand(MI, AMDGPU::OpName::src0),
- getNamedOperand(MI, AMDGPU::OpName::src1),
- getNamedOperand(MI, AMDGPU::OpName::src2)};
- const unsigned Mods[3] = {
- static_cast<unsigned>(
- getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm()),
- static_cast<unsigned>(
- getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm()),
- static_cast<unsigned>(
- getNamedOperand(MI, AMDGPU::OpName::src2_modifiers)->getImm())};
-
- // extract op_sel / op_sel_hi
- bool OpSel[3][2];
- for (unsigned I = 0; I != 3; ++I) {
- OpSel[I][0] = Mods[I] & SISrcMods::OP_SEL_0;
- OpSel[I][1] = Mods[I] & SISrcMods::OP_SEL_1;
- }
-
- // The packed op can read only one SGPR on the constant bus (limit is 1 on
- // gfx9), so all its SGPR sources are the same pair. Each scalar lane can also
- // read only one SGPR, but op_sel may make a lane read
diff erent halves of
- // that pair, e.g.
- // v_pk_fma_f32 v[0:1], s[0:1], 0, s[0:1] op_sel:[0,0,1] op_sel_hi:[1,1,0]
- // => v_fma_f32 v0, s0, 0, s1 / v_fma_f32 v1, s1, 0, s0
- // If so, copy the pair to a VGPR once before extracting the lanes, rather
- // than moving a scalar into a VGPR per lane.
- SmallVector<unsigned, 3> SGPRSrcs;
- bool DivergentSGPRs = false;
- for (unsigned I = 0; I != 3; ++I) {
- if (!Srcs[I]->isReg() || !RI.isSGPRReg(MRI, Srcs[I]->getReg()))
- continue;
- if (!SGPRSrcs.empty()) {
- unsigned First = SGPRSrcs.front();
- assert(Srcs[I]->getReg() == Srcs[First]->getReg() &&
- Srcs[I]->getSubReg() == Srcs[First]->getSubReg() &&
- "constant bus limit allows only one SGPR source");
- DivergentSGPRs |=
- OpSel[I][0] != OpSel[First][0] || OpSel[I][1] != OpSel[First][1];
- }
- SGPRSrcs.push_back(I);
- }
-
- if (DivergentSGPRs) {
- unsigned First = SGPRSrcs.front();
- legalizeOpWithMove(MI, MI.getOperandNo(Srcs[First]));
- for (unsigned I : ArrayRef(SGPRSrcs).drop_front())
- Srcs[I]->ChangeToRegister(Srcs[First]->getReg(), /*isDef=*/false);
- }
-
- // Extract the low or high lane of a packed VOP3P source operand.
- auto ExtractLane = [&](MachineOperand &Op, bool UseSub1) -> MachineOperand {
- unsigned SubIdx = (Op.isReg() && UseSub1) ? AMDGPU::sub1 : AMDGPU::sub0;
- const TargetRegisterClass *RC =
- Op.isReg() ? MRI.getRegClass(Op.getReg()) : nullptr;
- const TargetRegisterClass *SubRC = !Op.isReg() ? nullptr
- : RI.isVGPR(MRI, Op.getReg())
- ? RI.getVGPRClassForBitWidth(32)
- : RI.getSGPRClassForBitWidth(32);
- return buildExtractSubRegOrImm(MI, MRI, Op, RC, SubIdx, SubRC);
- };
-
- // neg_lo/neg_hi on the packed operand become a plain NEG modifier.
- auto LaneMods = [](unsigned Mods, bool Hi) -> unsigned {
- if (Hi)
- return (Mods & SISrcMods::NEG_HI) ? static_cast<unsigned>(SISrcMods::NEG)
- : 0u;
- return Mods & SISrcMods::NEG;
- };
-
- auto BuildLane = [&](Register Dst, bool Hi) {
- MachineOperand L0 = ExtractLane(*Srcs[0], OpSel[0][Hi]);
- MachineOperand L1 = ExtractLane(*Srcs[1], OpSel[1][Hi]);
- MachineOperand L2 = ExtractLane(*Srcs[2], OpSel[2][Hi]);
- BuildMI(MBB, MI, DL, get(AMDGPU::V_FMA_F32_e64), Dst)
- .addImm(LaneMods(Mods[0], Hi))
- .add(L0)
- .addImm(LaneMods(Mods[1], Hi))
- .add(L1)
- .addImm(LaneMods(Mods[2], Hi))
- .add(L2)
- .addImm(0) // clamp
- .addImm(0); // omod
- };
-
- const TargetRegisterClass *VGPR32 = RI.getVGPRClassForBitWidth(32);
- Register Lo = MRI.createVirtualRegister(VGPR32);
- Register Hi = MRI.createVirtualRegister(VGPR32);
- BuildLane(Lo, false);
- BuildLane(Hi, true);
-
- Register Dst = getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg();
- BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
- .addReg(Lo)
- .addImm(AMDGPU::sub0)
- .addReg(Hi)
- .addImm(AMDGPU::sub1);
-
- MI.eraseFromParent();
-}
-
bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
const MachineOperand *MO) const {
const MachineFunction &MF = *MI.getMF();
@@ -7276,13 +7151,6 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
legalizeOpWithMove(MI, VOP3Idx[I]);
}
}
-
- // Fix GFX950 v_pk_fma_f32 invalid op_sel by decomposing.
- if (ST.hasPkF32InvalidOpSel() && Opc == AMDGPU::V_PK_FMA_F32 &&
- !isLegalPkFMAF32OpSel(MI)) {
- decomposePkFMAF32(MI, MRI);
- return;
- }
}
Register SIInstrInfo::readlaneVGPRToSGPR(
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index b3c89101f9250a..852f3d811c2a2d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1560,13 +1560,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
const MachineInstr &MI, unsigned SrcN,
const MachineOperand *MO = nullptr) const;
- /// Check if \p MI has legal GFX950 v_pk_fma op_sel.
- bool isLegalPkFMAF32OpSel(const MachineInstr &MI) const;
-
- /// Decompose a GFX950 v_pk_fma_f32 with invalid op_sel into two independent
- /// scalar V_FMA_F32_e64 instructions, replacing \p MI.
- void decomposePkFMAF32(MachineInstr &MI, MachineRegisterInfo &MRI) const;
-
/// Legalize operands in \p MI by either commuting it or inserting a
/// copy of src1.
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
diff --git a/llvm/test/CodeGen/AMDGPU/gfx950-pk-f32-invalid-op-sel.ll b/llvm/test/CodeGen/AMDGPU/gfx950-pk-f32-invalid-op-sel.ll
deleted file mode 100644
index c0a3301bca9461..00000000000000
--- a/llvm/test/CodeGen/AMDGPU/gfx950-pk-f32-invalid-op-sel.ll
+++ /dev/null
@@ -1,719 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -stop-after=finalize-isel < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgpu9.50-amd-amdhsa -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL %s
-; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck -check-prefix=ASM %s
-; RUN: llc -global-isel -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck -check-prefix=ASM %s
-
-; GFX950 v_pk_{add,mul,fma}_f32 has several invalid opsels.
-; case1: opsel[1:0]==2’b10 : Packed ADD_F32/MUL_F32
-; case2: opsel[2:1]==2'b01/2'b10/2'b11 : Packed FMA_F32
-
-define amdgpu_kernel void @case1_add_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
- ; GCN-LABEL: name: case1_add_f32
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.b, addrspace 1)
- ; GCN-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_ADD_F32 8, [[GLOBAL_LOAD_DWORDX2_SADDR]], 4, [[GLOBAL_LOAD_DWORDX2_SADDR1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[V_PK_ADD_F32_]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case1_add_f32
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.b, addrspace 1)
- ; GISEL-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_ADD_F32 8, [[GLOBAL_LOAD_DWORDX2_SADDR]], 4, [[GLOBAL_LOAD_DWORDX2_SADDR1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[V_PK_ADD_F32_]], [[COPY7]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %gep.b0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %gep.b = getelementptr i8, ptr addrspace(1) %gep.b0, i64 1024
- %b = load <2 x float>, ptr addrspace(1) %gep.b
- %shuf.b = shufflevector <2 x float> %b, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %r = fadd <2 x float> %a, %shuf.b
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-define amdgpu_kernel void @case1_mul_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
- ; GCN-LABEL: name: case1_mul_f32
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.b, addrspace 1)
- ; GCN-NEXT: [[V_PK_MUL_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, [[GLOBAL_LOAD_DWORDX2_SADDR]], 4, [[GLOBAL_LOAD_DWORDX2_SADDR1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[V_PK_MUL_F32_]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case1_mul_f32
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.b, addrspace 1)
- ; GISEL-NEXT: [[V_PK_MUL_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_MUL_F32 8, [[GLOBAL_LOAD_DWORDX2_SADDR]], 4, [[GLOBAL_LOAD_DWORDX2_SADDR1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[V_PK_MUL_F32_]], [[COPY7]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %gep.b0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %gep.b = getelementptr i8, ptr addrspace(1) %gep.b0, i64 1024
- %b = load <2 x float>, ptr addrspace(1) %gep.b
- %shuf.b = shufflevector <2 x float> %b, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %r = fmul <2 x float> %a, %shuf.b
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-define amdgpu_kernel void @case2_fma_f32_opsel010(ptr addrspace(1) %out, ptr addrspace(1) %in) {
- ; GCN-LABEL: name: case2_fma_f32_opsel010
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.b, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR2:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 2048, 0, implicit $exec :: (load (s64) from %ir.gep.c, addrspace 1)
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub0
- ; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY6]], 0, [[COPY7]], 0, [[COPY8]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GCN-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GCN-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub1
- ; GCN-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY9]], 0, [[COPY10]], 0, [[COPY11]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case2_fma_f32_opsel010
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.b, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR2:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 2048, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.c, addrspace 1)
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub0
- ; GISEL-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY7]], 0, [[COPY8]], 0, [[COPY9]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GISEL-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GISEL-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub1
- ; GISEL-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY10]], 0, [[COPY11]], 0, [[COPY12]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GISEL-NEXT: [[COPY13:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE]], [[COPY13]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %gep.b0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %gep.b = getelementptr i8, ptr addrspace(1) %gep.b0, i64 1024
- %b = load <2 x float>, ptr addrspace(1) %gep.b
- %gep.c = getelementptr i8, ptr addrspace(1) %gep.b0, i64 2048
- %c = load <2 x float>, ptr addrspace(1) %gep.c
- %shuf.b = shufflevector <2 x float> %b, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %r = call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %shuf.b, <2 x float> %c)
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-define amdgpu_kernel void @case2_fma_f32_opsel100(ptr addrspace(1) %out, ptr addrspace(1) %in, <2 x float> %s) {
- ; GCN-LABEL: name: case2_fma_f32_opsel100
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 16, 0 :: (dereferenceable invariant load (s64) from %ir.s.kernarg.offset, align 16, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.c, addrspace 1)
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY6]], 0, [[COPY7]], 0, [[COPY8]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GCN-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
- ; GCN-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GCN-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY9]], 0, [[COPY10]], 0, [[COPY11]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case2_fma_f32_opsel100
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 16, 0 :: (dereferenceable invariant load (<2 x f32>) from %ir.s.kernarg.offset, align 16, addrspace 4)
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.c, addrspace 1)
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vreg_64_align2 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
- ; GISEL-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GISEL-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY8]], 0, [[COPY9]], 0, [[COPY10]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GISEL-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
- ; GISEL-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GISEL-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY11]], 0, [[COPY12]], 0, [[COPY13]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GISEL-NEXT: [[COPY14:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE]], [[COPY14]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %gep.c0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %gep.c = getelementptr i8, ptr addrspace(1) %gep.c0, i64 1024
- %c0 = load <2 x float>, ptr addrspace(1) %gep.c
- %shuf.c = shufflevector <2 x float> %c0, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %r = call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %s, <2 x float> %shuf.c)
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-define amdgpu_kernel void @case2_fma_f32_opsel110(ptr addrspace(1) %out, ptr addrspace(1) %in) {
- ; GCN-LABEL: name: case2_fma_f32_opsel110
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.b, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR2:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 2048, 0, implicit $exec :: (load (s64) from %ir.gep.c, addrspace 1)
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub1
- ; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY6]], 0, [[COPY7]], 0, [[COPY8]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GCN-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GCN-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub0
- ; GCN-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY9]], 0, [[COPY10]], 0, [[COPY11]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case2_fma_f32_opsel110
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.b, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR2:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 2048, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.c, addrspace 1)
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub1
- ; GISEL-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY7]], 0, [[COPY8]], 0, [[COPY9]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GISEL-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GISEL-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub0
- ; GISEL-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY10]], 0, [[COPY11]], 0, [[COPY12]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GISEL-NEXT: [[COPY13:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE]], [[COPY13]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %gep.b0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %gep.b = getelementptr i8, ptr addrspace(1) %gep.b0, i64 1024
- %b = load <2 x float>, ptr addrspace(1) %gep.b
- %gep.c = getelementptr i8, ptr addrspace(1) %gep.b0, i64 2048
- %c = load <2 x float>, ptr addrspace(1) %gep.c
- %shuf.b = shufflevector <2 x float> %b, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %shuf.c = shufflevector <2 x float> %c, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %r = call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %shuf.b, <2 x float> %shuf.c)
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-define amdgpu_kernel void @case2_fma_f32_opsel101(ptr addrspace(1) %out, ptr addrspace(1) %in) {
- ; GCN-LABEL: name: case2_fma_f32_opsel101
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.b, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR2:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 2048, 0, implicit $exec :: (load (s64) from %ir.gep.c, addrspace 1)
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub1
- ; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY6]], 0, [[COPY7]], 0, [[COPY8]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GCN-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GCN-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub0
- ; GCN-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY9]], 0, [[COPY10]], 0, [[COPY11]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case2_fma_f32_opsel101
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.b, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR2:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 2048, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.c, addrspace 1)
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub1
- ; GISEL-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY7]], 0, [[COPY8]], 0, [[COPY9]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GISEL-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GISEL-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR2]].sub0
- ; GISEL-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY10]], 0, [[COPY11]], 0, [[COPY12]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GISEL-NEXT: [[COPY13:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE]], [[COPY13]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %gep.b0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %gep.b = getelementptr i8, ptr addrspace(1) %gep.b0, i64 1024
- %b = load <2 x float>, ptr addrspace(1) %gep.b
- %gep.c = getelementptr i8, ptr addrspace(1) %gep.b0, i64 2048
- %c = load <2 x float>, ptr addrspace(1) %gep.c
- %shuf.a = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %shuf.c = shufflevector <2 x float> %c, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %r = call <2 x float> @llvm.fma.v2f32(<2 x float> %shuf.a, <2 x float> %b, <2 x float> %shuf.c)
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-define amdgpu_kernel void @case2_fma_f32_imm_neg(ptr addrspace(1) %out, ptr addrspace(1) %in) {
- ; GCN-LABEL: name: case2_fma_f32_imm_neg
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a0, addrspace 1)
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (s64) from %ir.gep.c0, addrspace 1)
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY6]], 0, -1082130432, 1, [[COPY7]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GCN-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY8]], 0, -1082130432, 1, [[COPY9]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case2_fma_f32_imm_neg
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1065353216
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_2]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a0, addrspace 1)
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR1:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 1024, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.c0, addrspace 1)
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub0
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
- ; GISEL-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub1
- ; GISEL-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 1, [[COPY8]], 0, [[COPY9]], 1, [[COPY10]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR]].sub1
- ; GISEL-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
- ; GISEL-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_SADDR1]].sub0
- ; GISEL-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 1, [[COPY11]], 0, [[COPY12]], 1, [[COPY13]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GISEL-NEXT: [[COPY14:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a0 = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a0 = load <2 x float>, ptr addrspace(1) %gep.a0
- %a = fneg <2 x float> %a0
- %gep.c0 = getelementptr i8, ptr addrspace(1) %gep.a0, i64 1024
- %c0 = load <2 x float>, ptr addrspace(1) %gep.c0
- %shuf.c0 = shufflevector <2 x float> %c0, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %c = fneg <2 x float> %shuf.c0
- %r = call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> %c)
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-; Not Case 2: opsel[2:0]==3'b000.
-define amdgpu_kernel void @not_case2_fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %in, <2 x float> %s) {
- ; GCN-LABEL: name: not_case2_fma_f32
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
- ; GCN-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s128) from %ir.out.kernarg.offset1, addrspace 4)
- ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 16, 0 :: (dereferenceable invariant load (s64) from %ir.s.kernarg.offset, align 16, addrspace 4)
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub0
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]](i32), [[S_MOV_B32_]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 [[S_MOV_B32_1]], [[V_AND_B32_e64_]], implicit $exec
- ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.gep.a, addrspace 1)
- ; GCN-NEXT: [[V_PK_FMA_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_FMA_F32 8, [[GLOBAL_LOAD_DWORDX2_SADDR]], 8, [[S_LOAD_DWORDX2_IMM]], 0, 1065353216, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[V_PK_FMA_F32_]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (store (s64) into %ir.gep.out, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: not_case2_fma_f32
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5, $vgpr0
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1065353216
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
- ; GISEL-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x i64>) from %ir.out.kernarg.offset1, addrspace 4)
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
- ; GISEL-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 16, 0 :: (dereferenceable invariant load (<2 x f32>) from %ir.s.kernarg.offset, align 16, addrspace 4)
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GISEL-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY4]], implicit $exec
- ; GISEL-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_2]]
- ; GISEL-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY5]], [[V_AND_B32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY3]]
- ; GISEL-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2_SADDR [[COPY6]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (<2 x f32>) from %ir.gep.a, addrspace 1)
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vreg_64_align2 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]
- ; GISEL-NEXT: [[V_PK_FMA_F32_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_FMA_F32 8, [[GLOBAL_LOAD_DWORDX2_SADDR]], 8, [[COPY7]], 8, [[COPY8]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY2]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_LSHLREV_B32_e64_]], [[V_PK_FMA_F32_]], [[COPY9]], 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.gep.out, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %tid = call i32 @llvm.amdgcn.workitem.id.x()
- %idx = zext i32 %tid to i64
- %gep.a = getelementptr <2 x float>, ptr addrspace(1) %in, i64 %idx
- %a = load <2 x float>, ptr addrspace(1) %gep.a
- %r = call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %s, <2 x float> <float 1.000000e+00, float 1.000000e+00>)
- %gep.out = getelementptr <2 x float>, ptr addrspace(1) %out, i64 %idx
- store <2 x float> %r, ptr addrspace(1) %gep.out
- ret void
-}
-
-; The packed FMA reads the same SGPR pair as src0 and src2 with opposite halves
-; selected, so it needs only one constant bus read. Once decomposed, each scalar
-; lane reads two
diff erent SGPRs, which has to be legalized to respect the constant bus limit.
-define amdgpu_kernel void @case2_fma_f32_two_sgpr_lanes(<2 x float> %x) {
- ; GCN-LABEL: name: case2_fma_f32_two_sgpr_lanes
- ; GCN: bb.0.entry:
- ; GCN-NEXT: liveins: $sgpr4_sgpr5
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
- ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s64) from %ir.x.kernarg.offset1, align 16, addrspace 4)
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1082130432
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 1073741824
- ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
- ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
- ; GCN-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY4]], 0, [[COPY5]], 1, [[COPY6]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
- ; GCN-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY7]], 0, [[COPY8]], 1, [[COPY9]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GCN-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
- ; GCN-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
- ; GCN-NEXT: [[V_CVT_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY11]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[V_CVT_F16_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY10]], 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_CVT_F16_F32_e64_]], [[V_CVT_F16_F32_e64_1]], implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
- ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[V_OR_B32_e64_]], [[S_MOV_B32_2]], implicit $exec
- ; GCN-NEXT: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 0, implicit $exec
- ; GCN-NEXT: [[COPY12:%[0-9]+]]:av_32 = COPY [[V_AND_B32_e64_]]
- ; GCN-NEXT: GLOBAL_STORE_DWORD [[V_MOV_B64_e32_]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) null`, addrspace 1)
- ; GCN-NEXT: S_ENDPGM 0
- ;
- ; GISEL-LABEL: name: case2_fma_f32_two_sgpr_lanes
- ; GISEL: bb.1.entry:
- ; GISEL-NEXT: liveins: $sgpr4_sgpr5
- ; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
- ; GISEL-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1082130432
- ; GISEL-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824
- ; GISEL-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
- ; GISEL-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (<2 x f32>) from %ir.x.kernarg.offset1, align 16, addrspace 4)
- ; GISEL-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; GISEL-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
- ; GISEL-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
- ; GISEL-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
- ; GISEL-NEXT: [[V_FMA_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY4]], 0, [[COPY5]], 1, [[COPY6]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
- ; GISEL-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub1
- ; GISEL-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
- ; GISEL-NEXT: [[V_FMA_F32_e64_1:%[0-9]+]]:vgpr_32 = V_FMA_F32_e64 0, [[COPY7]], 0, [[COPY8]], 1, [[COPY9]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_FMA_F32_e64_]], %subreg.sub0, [[V_FMA_F32_e64_1]], %subreg.sub1
- ; GISEL-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
- ; GISEL-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
- ; GISEL-NEXT: [[V_CVT_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY11]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[V_CVT_F16_F32_e64_]], implicit $exec
- ; GISEL-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GISEL-NEXT: [[V_CVT_F16_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY10]], 0, 0, implicit $mode, implicit $exec
- ; GISEL-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[V_CVT_F16_F32_e64_1]], implicit $exec
- ; GISEL-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GISEL-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY12]], [[COPY13]], implicit-def dead $scc
- ; GISEL-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
- ; GISEL-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_OR_B32_]], implicit-def dead $scc
- ; GISEL-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
- ; GISEL-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
- ; GISEL-NEXT: [[COPY15:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B]]
- ; GISEL-NEXT: GLOBAL_STORE_DWORD [[COPY15]], [[COPY14]], 0, 0, implicit $exec :: (store (i32) into `ptr addrspace(1) null`, addrspace 1)
- ; GISEL-NEXT: S_ENDPGM 0
-entry:
- %m = fmul contract <2 x float> %x, <float 2.000000e+00, float 4.000000e+00>
- %s = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> <i32 1, i32 0>
- %d = fsub contract <2 x float> %m, %s
- %lo = extractelement <2 x float> %d, i64 0
- %hi = extractelement <2 x float> %d, i64 1
- %hh = fptrunc float %hi to half
- %hb = bitcast half %hh to i16
- %lh = fptrunc float %lo to half
- %lb = bitcast half %lh to i16
- %o = or i16 %hb, %lb
- %z = zext i16 %o to i32
- store i32 %z, ptr addrspace(1) null, align 4
- ret void
-}
-
-; final-assembly checks: confirm GCNHazardRecognizer::fixPkF32InvalidOpSel
-; commutes each bad opsel[1:0]==2'b10 ADD/MUL shape into the safe encoding
-; (regardless of SRC0/SRC1 register class), identically for SelectionDAG and
-; GlobalISel.
-
-; ASM-LABEL: case1_add_f32:
-; ASM: v_pk_add_f32 v[0:1], v[2:3], v[0:1] op_sel:[1,0] op_sel_hi:[0,1]
-
-; ASM-LABEL: case1_mul_f32:
-; ASM: v_pk_mul_f32 v[0:1], v[2:3], v[0:1] op_sel:[1,0] op_sel_hi:[0,1]
-
-; ASM-LABEL: case2_fma_f32_opsel010:
-; ASM: v_fma_f32 v0, v0, v3, v4
-; ASM: v_fma_f32 v1, v1, v2, v5
-
-; ASM-LABEL: case2_fma_f32_opsel110:
-; ASM: v_fma_f32 v0, v0, v3, v5
-; ASM: v_fma_f32 v1, v1, v2, v4
-
-; ASM-LABEL: case2_fma_f32_opsel101:
-; ASM: v_fma_f32 v2, v1, v2, v5
-; ASM: v_fma_f32 v3, v0, v3, v4
-
-; ASM-LABEL: not_case2_fma_f32:
-; ASM: v_pk_fma_f32 v[0:1], v[0:1], s[6:7], 1.0
-
-; ASM-LABEL: case2_fma_f32_two_sgpr_lanes:
-; ASM-NOT: v_pk_fma_f32
-; ASM: v_fma_f32 v{{[0-9]+}}, {{[sv][0-9]+}}, {{([sv][0-9]+|[0-9.]+)}}, -v{{[0-9]+}}
-; ASM: v_fma_f32 v{{[0-9]+}}, {{[sv][0-9]+}}, {{([sv][0-9]+|[0-9.]+)}}, -v{{[0-9]+}}
-; ASM-NOT: v_pk_fma_f32
diff --git a/llvm/test/MC/AMDGPU/gfx950_err.s b/llvm/test/MC/AMDGPU/gfx950_err.s
index 4eba422dc704dd..41bf59cac53620 100644
--- a/llvm/test/MC/AMDGPU/gfx950_err.s
+++ b/llvm/test/MC/AMDGPU/gfx950_err.s
@@ -486,27 +486,3 @@ v_pk_maximum3_f16 v0, s1, s2, v3
v_pk_minimum3_f16 v0, s1, s2, v3
// GFX950: :[[@LINE-1]]:27: error: invalid operand (violates constant bus restrictions)
-
-v_pk_add_f32 v[4:5], v[8:9], v[16:17] op_sel:[0,1]
-// GFX950: :[[@LINE-1]]:39: error: invalid op_sel operand
-
-v_pk_mul_f32 v[4:5], v[8:9], v[16:17] op_sel:[0,1]
-// GFX950: :[[@LINE-1]]:39: error: invalid op_sel operand
-
-v_pk_fma_f32 v[8:9], v[0:1], v[2:3], v[4:5] op_sel:[0,1,0]
-// GFX950: :[[@LINE-1]]:45: error: invalid op_sel operand
-
-v_pk_fma_f32 v[8:9], v[0:1], v[2:3], v[4:5] op_sel:[0,0,1]
-// GFX950: :[[@LINE-1]]:45: error: invalid op_sel operand
-
-v_pk_fma_f32 v[8:9], v[0:1], v[2:3], v[4:5] op_sel:[0,1,1]
-// GFX950: :[[@LINE-1]]:45: error: invalid op_sel operand
-
-v_pk_fma_f32 v[8:9], v[0:1], v[2:3], v[4:5] op_sel:[1,1,0]
-// GFX950: :[[@LINE-1]]:45: error: invalid op_sel operand
-
-v_pk_fma_f32 v[8:9], v[0:1], v[2:3], v[4:5] op_sel:[1,0,1]
-// GFX950: :[[@LINE-1]]:45: error: invalid op_sel operand
-
-v_pk_fma_f32 v[8:9], v[0:1], v[2:3], v[4:5] op_sel:[1,1,1]
-// GFX950: :[[@LINE-1]]:45: error: invalid op_sel operand
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