[llvm-branch-commits] [llvm] CodeGen: Strip LiveVariables down to dead flag computation (PR #230149)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Oct 8 10:48:52 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/230149
>From 4791c59f46ca256e8879d22a4842febb062e12cc Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 8 Oct 2026 15:46:43 +0200
Subject: [PATCH] CodeGen: Strip LiveVariables down to dead flag computation
This analysis is dead and there are no more explicit uses. There are still
passes implicitly relying on adjustments of dead flags. Missing dead
flags are added, and implicit-def operands are added for partially dead
physical registers.
The whole pass should be deleted, but it's taking a while to get all the dead
flag changes through the rest of the compiler. As a stop-gap to try to recover
some compile time regression, and avoiding new users appearing, strip the pass
down to only commputing the dead flags.
The main side effect of this is kill flags are no longer made accurate, which
is the source of the test churn.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
llvm/include/llvm/CodeGen/LiveVariables.h | 238 +-------
llvm/include/llvm/CodeGen/Passes.h | 3 +-
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 1 -
.../llvm/Passes/MachinePassRegistry.def | 1 -
llvm/lib/CodeGen/LiveVariables.cpp | 572 ++----------------
.../AArch64/GlobalISel/arm64-pcsections.ll | 32 +-
.../CodeGen/AArch64/misched-fusion-csel.ll | 4 +-
.../CodeGen/AMDGPU/livevars-implicitdef.mir | 16 +-
.../llvm.amdgcn.ds.gws.barrier-bundle.ll | 8 +-
.../CodeGen/AMDGPU/no-fold-accvgpr-mov.mir | 12 +-
.../CodeGen/AMDGPU/no-fold-accvgpr-read.mir | 4 +-
.../CodeGen/AMDGPU/phi-elim-mli-available.mir | 18 +-
.../AMDGPU/phi-elimination-assertion.mir | 4 +-
.../CodeGen/AMDGPU/phi-elimination-end-cf.mir | 2 +-
.../rewrite-mfma-form-spill-cost-reset.ll | 2 +-
llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll | 2 +-
llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll | 10 +-
.../waterfall-loop-exec-update-terminator.mir | 52 +-
.../CodeGen/PowerPC/2013-07-01-PHIElimBug.mir | 2 +-
llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll | 68 +--
llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll | 8 +-
.../CodeGen/PowerPC/aix-cc-byval-split.ll | 2 +-
.../CodeGen/PowerPC/aix-vec-arg-spills-mir.ll | 4 +-
llvm/test/CodeGen/PowerPC/mflr-store.mir | 2 +-
.../test/CodeGen/SystemZ/regcoal_undefsrc.mir | 2 +-
llvm/test/CodeGen/X86/AMX/amx-greedy-ra.ll | 2 +-
llvm/test/CodeGen/X86/epilogue-cfi-fp.ll | 2 +-
llvm/test/CodeGen/X86/live-vars.ll | 27 -
.../CodeGen/X86/lvi-hardening-gadget-graph.ll | 4 +-
.../CodeGen/X86/phi-elim-undef-livevars.mir | 8 +-
llvm/test/CodeGen/X86/pr58914.mir | 6 +-
.../statepoint-cmp-sunk-past-statepoint.ll | 8 +-
llvm/test/CodeGen/X86/statepoint-ra.ll | 6 +-
.../CodeGen/X86/statepoint-vreg-invoke.ll | 4 +-
.../statepoint-vreg-unlimited-tied-opnds.ll | 2 +-
.../X86/two-address-subreg-to-reg-kill.mir | 8 +-
llvm/unittests/MI/LiveIntervalTest.cpp | 64 --
37 files changed, 213 insertions(+), 997 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/live-vars.ll
diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h
index 4b06c5b48335f..99fc2eadc1d22 100644
--- a/llvm/include/llvm/CodeGen/LiveVariables.h
+++ b/llvm/include/llvm/CodeGen/LiveVariables.h
@@ -6,22 +6,9 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements the LiveVariables analysis pass. For each machine
-// instruction in the function, this pass calculates the set of registers that
-// are immediately dead after the instruction (i.e., the instruction calculates
-// the value, but it is never used) and the set of registers that are used by
-// the instruction, but are never used after the instruction (i.e., they are
-// killed).
-//
-// This class computes live variables using a sparse implementation based on
-// the machine code SSA form. This class computes live variable information for
-// each virtual and _register allocatable_ physical register in a function. It
-// uses the dominance properties of SSA form to efficiently compute live
-// variables for virtual registers, and assumes that physical registers are only
-// live within a single basic block (allowing it to do a single local analysis
-// to resolve physical register lifetimes in each basic block). If a physical
-// register is not register allocatable, it is not tracked. This is useful for
-// things like the stack pointer and condition codes.
+// This is a defunct analysis and should not be used. This pass should be
+// deleted. It's sole function is now to made adjustments to dead flags and
+// should be deleted once later passes are fixed.
//
//===----------------------------------------------------------------------===//
@@ -29,10 +16,7 @@
#define LLVM_CODEGEN_LIVEVARIABLES_H
#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/IndexedMap.h"
-#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachinePassManager.h"
@@ -48,79 +32,6 @@ class MachineRegisterInfo;
class LiveVariables {
friend class LiveVariablesWrapperPass;
-public:
- /// VarInfo - This represents the regions where a virtual register is live in
- /// the program. We represent this with three different pieces of
- /// information: the set of blocks in which the instruction is live
- /// throughout, the set of blocks in which the instruction is actually used,
- /// and the set of non-phi instructions that are the last users of the value.
- ///
- /// In the common case where a value is defined and killed in the same block,
- /// There is one killing instruction, and AliveBlocks is empty.
- ///
- /// Otherwise, the value is live out of the block. If the value is live
- /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
- /// where the liveness range ends are not included in AliveBlocks, instead
- /// being captured by the Kills set. In these blocks, the value is live into
- /// the block (unless the value is defined and killed in the same block) and
- /// lives until the specified instruction. Note that there cannot ever be a
- /// value whose Kills set contains two instructions from the same basic block.
- ///
- /// PHI nodes complicate things a bit. If a PHI node is the last user of a
- /// value in one of its predecessor blocks, it is not listed in the kills set,
- /// but does include the predecessor block in the AliveBlocks set (unless that
- /// block also defines the value). This leads to the (perfectly sensical)
- /// situation where a value is defined in a block, and the last use is a phi
- /// node in the successor. In this case, AliveBlocks is empty (the value is
- /// not live across any blocks) and Kills is empty (phi nodes are not
- /// included). This is sensical because the value must be live to the end of
- /// the block, but is not live in any successor blocks.
- struct VarInfo {
- /// AliveBlocks - Set of blocks in which this value is alive completely
- /// through. This is a bit set which uses the basic block number as an
- /// index.
- ///
- SparseBitVector<> AliveBlocks;
-
- /// Kills - List of MachineInstruction's which are the last use of this
- /// virtual register (kill it) in their basic block.
- ///
- std::vector<MachineInstr*> Kills;
-
- /// removeKill - Delete a kill corresponding to the specified
- /// machine instruction. Returns true if there was a kill
- /// corresponding to this instruction, false otherwise.
- bool removeKill(MachineInstr &MI) {
- std::vector<MachineInstr *>::iterator I = find(Kills, &MI);
- if (I == Kills.end())
- return false;
- Kills.erase(I);
- return true;
- }
-
- /// findKill - Find a kill instruction in MBB. Return NULL if none is found.
- LLVM_ABI MachineInstr *findKill(const MachineBasicBlock *MBB) const;
-
- /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
- /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
- /// MBB, it is not considered live in.
- LLVM_ABI bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
- MachineRegisterInfo &MRI);
-
- LLVM_ABI void print(raw_ostream &OS) const;
-
- LLVM_ABI void dump() const;
- };
-
-private:
- /// VirtRegInfo - This list is a mapping from virtual register number to
- /// variable information.
- ///
- IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
-
-private: // Intermediate data structures
- MachineFunction *MF = nullptr;
-
MachineRegisterInfo *MRI = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -135,8 +46,6 @@ class LiveVariables {
// register references are presumed dead across basic blocks.
std::vector<MachineInstr *> PhysRegUse;
- std::vector<SmallVector<Register, 4>> PHIVarInfo;
-
// DistanceMap - Keep track the distance of a MI from the start of the
// current basic block.
DenseMap<MachineInstr*, unsigned> DistanceMap;
@@ -146,10 +55,10 @@ class LiveVariables {
LLVM_ABI void analyze(MachineFunction &MF);
- /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
- /// uses. Pay special attention to the sub-register uses which may come below
- /// the last use of the whole register.
- bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
+ /// HandlePhysRegKill - Mark the last def of Reg and its sub-registers dead
+ /// if they are not used. Pay special attention to the sub-register uses
+ /// which may come below the last use of the whole register.
+ void HandlePhysRegKill(Register Reg, MachineInstr *MI);
/// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
void HandleRegMask(const MachineOperand &, unsigned);
@@ -167,12 +76,6 @@ class LiveVariables {
/// register.
MachineInstr *FindLastPartialDef(Register Reg);
- /// analyzePHINodes - Gather information about the PHI nodes in here. In
- /// particular, we want to map the variable information of a virtual
- /// register which is used in a PHI node. We map that to the BB the vreg
- /// is coming from.
- void analyzePHINodes(const MachineFunction& Fn);
-
void runOnInstr(MachineInstr &MI, SmallVectorImpl<Register> &Defs,
unsigned NumRegs);
@@ -180,119 +83,6 @@ class LiveVariables {
public:
LLVM_ABI LiveVariables(MachineFunction &MF);
-
- LLVM_ABI void print(raw_ostream &OS) const;
-
- //===--------------------------------------------------------------------===//
- // API to update live variable information
-
- /// Recompute liveness from scratch for a virtual register \p Reg that is
- /// known to have a single def that dominates all uses. This can be useful
- /// after removing some uses of \p Reg. It is not necessary for the whole
- /// machine function to be in SSA form.
- LLVM_ABI void recomputeForSingleDefVirtReg(Register Reg);
-
- /// addVirtualRegisterKilled - Add information about the fact that the
- /// specified register is killed after being used by the specified
- /// instruction. If AddIfNotFound is true, add a implicit operand if it's
- /// not found.
- void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI,
- bool AddIfNotFound = false) {
- if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
- getVarInfo(IncomingReg).Kills.push_back(&MI);
- }
-
- /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
- /// register from the live variable information. Returns true if the
- /// variable was marked as killed by the specified instruction,
- /// false otherwise.
- bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI) {
- if (!getVarInfo(Reg).removeKill(MI))
- return false;
-
- bool Removed = false;
- for (MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isKill() && MO.getReg() == Reg) {
- MO.setIsKill(false);
- Removed = true;
- break;
- }
- }
-
- assert(Removed && "Register is not used by this instruction!");
- (void)Removed;
- return true;
- }
-
- /// removeVirtualRegistersKilled - Remove all killed info for the specified
- /// instruction.
- LLVM_ABI void removeVirtualRegistersKilled(MachineInstr &MI);
-
- /// addVirtualRegisterDead - Add information about the fact that the specified
- /// register is dead after being used by the specified instruction. If
- /// AddIfNotFound is true, add a implicit operand if it's not found.
- void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI,
- bool AddIfNotFound = false) {
- if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound))
- getVarInfo(IncomingReg).Kills.push_back(&MI);
- }
-
- /// removeVirtualRegisterDead - Remove the specified kill of the virtual
- /// register from the live variable information. Returns true if the
- /// variable was marked dead at the specified instruction, false
- /// otherwise.
- bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI) {
- if (!getVarInfo(Reg).removeKill(MI))
- return false;
-
- bool Removed = false;
- for (MachineOperand &MO : MI.all_defs()) {
- if (MO.getReg() == Reg) {
- MO.setIsDead(false);
- Removed = true;
- break;
- }
- }
- assert(Removed && "Register is not defined by this instruction!");
- (void)Removed;
- return true;
- }
-
- /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
- /// register.
- LLVM_ABI VarInfo &getVarInfo(Register Reg);
-
- LLVM_ABI void MarkVirtRegAliveInBlock(VarInfo &VRInfo,
- MachineBasicBlock *DefBlock,
- MachineBasicBlock *BB);
- LLVM_ABI void
- MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *DefBlock,
- MachineBasicBlock *BB,
- SmallVectorImpl<MachineBasicBlock *> &WorkList);
-
- LLVM_ABI void HandleVirtRegDef(Register reg, MachineInstr &MI);
- LLVM_ABI void HandleVirtRegUse(Register reg, MachineBasicBlock *MBB,
- MachineInstr &MI);
-
- bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) {
- return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
- }
-
- /// isLiveOut - Determine if Reg is live out from MBB, when not considering
- /// PHI nodes. This means that Reg is either killed by a successor block or
- /// passed through one.
- LLVM_ABI bool isLiveOut(Register Reg, const MachineBasicBlock &MBB);
-
- /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
- /// variables that are live out of DomBB and live into SuccBB will be marked
- /// as passing live through BB. This method assumes that the machine code is
- /// still in SSA form.
- LLVM_ABI void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB,
- MachineBasicBlock *SuccBB);
-
- LLVM_ABI void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB,
- MachineBasicBlock *SuccBB,
- std::vector<SparseBitVector<>> &LiveInSets);
};
class LiveVariablesAnalysis : public AnalysisInfoMixin<LiveVariablesAnalysis> {
@@ -304,16 +94,6 @@ class LiveVariablesAnalysis : public AnalysisInfoMixin<LiveVariablesAnalysis> {
LLVM_ABI Result run(MachineFunction &MF, MachineFunctionAnalysisManager &);
};
-class LiveVariablesPrinterPass
- : public RequiredPassInfoMixin<LiveVariablesPrinterPass> {
- raw_ostream &OS;
-
-public:
- explicit LiveVariablesPrinterPass(raw_ostream &OS) : OS(OS) {}
- LLVM_ABI PreservedAnalyses run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM);
-};
-
class LLVM_ABI LiveVariablesWrapperPass : public MachineFunctionPass {
LiveVariables LV;
@@ -328,10 +108,6 @@ class LLVM_ABI LiveVariablesWrapperPass : public MachineFunctionPass {
}
void getAnalysisUsage(AnalysisUsage &AU) const override;
-
- void releaseMemory() override { LV.VirtRegInfo.clear(); }
-
- LiveVariables &getLV() { return LV; }
};
} // End llvm namespace
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 4eef016b0ee0a..95f95170456c8 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -150,8 +150,7 @@ LLVM_ABI extern char &MachineRegionInfoPassID;
/// EdgeBundles analysis - Bundle machine CFG edges.
LLVM_ABI extern char &EdgeBundlesWrapperLegacyID;
-/// LiveVariables pass - This pass computes the set of blocks in which each
-/// variable is life and sets machine operand kill flags.
+/// LiveVariables pass - This pass sets dead flags on register definitions.
LLVM_ABI extern char &LiveVariablesID;
/// PHIElimination - This pass eliminates machine instruction PHI nodes
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 3191b9e50a86d..e1fb7ef33de0f 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -44,7 +44,6 @@ namespace llvm {
class DFAPacketizer;
class InstrItineraryData;
class LiveIntervals;
-class LiveVariables;
class MachineCycleInfo;
class MachineLoop;
class MachineLoopInfo;
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 8713a4b6d26fd..ed582f2f61c65 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -119,7 +119,6 @@ MACHINE_FUNCTION_PASS("print<gisel-value-tracking>",
MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<live-stacks>", LiveStacksPrinterPass(errs()))
-MACHINE_FUNCTION_PASS("print<live-vars>", LiveVariablesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<machine-block-freq>",
MachineBlockFrequencyPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<machine-block-hash>",
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 5ce12c481bf16..af2ea6f9b8245 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -6,39 +6,27 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements the LiveVariable analysis pass. For each machine
-// instruction in the function, this pass calculates the set of registers that
-// are immediately dead after the instruction (i.e., the instruction calculates
-// the value, but it is never used) and the set of registers that are used by
-// the instruction, but are never used after the instruction (i.e., they are
-// killed).
+// This file implements the LiveVariable pass. For each machine instruction in
+// the function, this pass marks the registers that are immediately dead after
+// the instruction (i.e., the instruction calculates the value, but it is never
+// used). It does not compute kill flags or any queryable liveness information.
//
-// This class computes live variables using a sparse implementation based on
-// the machine code SSA form. This class computes live variable information for
-// each virtual and _register allocatable_ physical register in a function. It
-// uses the dominance properties of SSA form to efficiently compute live
-// variables for virtual registers, and assumes that physical registers are only
-// live within a single basic block (allowing it to do a single local analysis
-// to resolve physical register lifetimes in each basic block). If a physical
-// register is not register allocatable, it is not tracked. This is useful for
-// things like the stack pointer and condition codes.
+// A virtual register def is dead if the register has no reading uses. Physical
+// registers are assumed to only be live within a single basic block, and are
+// resolved with a local analysis of each block. This also adds implicit defs of
+// sub-registers and super-registers to model partially dead physical register
+// definitions. Reserved physical registers are not tracked.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/ADT/DenseSet.h"
-#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Config/llvm-config.h"
#include "llvm/InitializePasses.h"
-#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
using namespace llvm;
AnalysisKey LiveVariablesAnalysis::Key;
@@ -49,14 +37,6 @@ LiveVariablesAnalysis::run(MachineFunction &MF,
return Result(MF);
}
-PreservedAnalyses
-LiveVariablesPrinterPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- OS << "Live variables in machine function: " << MF.getName() << '\n';
- MFAM.getResult<LiveVariablesAnalysis>(MF).print(OS);
- return PreservedAnalyses::all();
-}
-
char LiveVariablesWrapperPass::ID = 0;
char &llvm::LiveVariablesID = LiveVariablesWrapperPass::ID;
INITIALIZE_PASS_BEGIN(LiveVariablesWrapperPass, "livevars",
@@ -71,147 +51,7 @@ void LiveVariablesWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-LiveVariables::LiveVariables(MachineFunction &MF)
- : MF(&MF), MRI(&MF.getRegInfo()), TRI(MF.getSubtarget().getRegisterInfo()) {
- analyze(MF);
-}
-
-void LiveVariables::print(raw_ostream &OS) const {
- for (size_t I = 0, E = VirtRegInfo.size(); I != E; ++I) {
- const Register Reg = Register::index2VirtReg(I);
- OS << "Virtual register '%" << I << "':\n";
- VirtRegInfo[Reg].print(OS);
- }
-}
-
-MachineInstr *
-LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
- for (MachineInstr *MI : Kills)
- if (MI->getParent() == MBB)
- return MI;
- return nullptr;
-}
-
-void LiveVariables::VarInfo::print(raw_ostream &OS) const {
- OS << " Alive in blocks: ";
- for (unsigned AB : AliveBlocks)
- OS << AB << ", ";
- OS << "\n Killed by:";
- if (Kills.empty())
- OS << " No instructions.\n\n";
- else {
- for (unsigned i = 0, e = Kills.size(); i != e; ++i)
- OS << "\n #" << i << ": " << *Kills[i];
- OS << "\n";
- }
-}
-
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const { print(dbgs()); }
-#endif
-
-/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
-LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) {
- assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");
- VirtRegInfo.grow(Reg);
- return VirtRegInfo[Reg];
-}
-
-void LiveVariables::MarkVirtRegAliveInBlock(
- VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB,
- SmallVectorImpl<MachineBasicBlock *> &WorkList) {
- unsigned BBNum = MBB->getNumber();
-
- // Check to see if this basic block is one of the killing blocks. If so,
- // remove it.
- for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
- if (VRInfo.Kills[i]->getParent() == MBB) {
- VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
- break;
- }
-
- if (MBB == DefBlock) return; // Terminate recursion
-
- if (VRInfo.AliveBlocks.test(BBNum))
- return; // We already know the block is live
-
- // Mark the variable known alive in this bb
- VRInfo.AliveBlocks.set(BBNum);
-
- assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
- WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
-}
-
-void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
- MachineBasicBlock *DefBlock,
- MachineBasicBlock *MBB) {
- SmallVector<MachineBasicBlock *, 16> WorkList;
- MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
-
- while (!WorkList.empty()) {
- MachineBasicBlock *Pred = WorkList.pop_back_val();
- MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
- }
-}
-
-void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB,
- MachineInstr &MI) {
- assert(MRI->getVRegDef(Reg) && "Register use before def!");
-
- unsigned BBNum = MBB->getNumber();
-
- VarInfo &VRInfo = getVarInfo(Reg);
-
- // Check to see if this basic block is already a kill block.
- if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
- // Yes, this register is killed in this basic block already. Increase the
- // live range by updating the kill instruction.
- VRInfo.Kills.back() = &MI;
- return;
- }
-
-#ifndef NDEBUG
- for (MachineInstr *Kill : VRInfo.Kills)
- assert(Kill->getParent() != MBB && "entry should be at end!");
-#endif
-
- // This situation can occur:
- //
- // ,------.
- // | |
- // | v
- // | t2 = phi ... t1 ...
- // | |
- // | v
- // | t1 = ...
- // | ... = ... t1 ...
- // | |
- // `------'
- //
- // where there is a use in a PHI node that's a predecessor to the defining
- // block. We don't want to mark all predecessors as having the value "alive"
- // in this case.
- if (MBB == MRI->getDefBlock(Reg))
- return;
-
- // Add a new kill entry for this basic block. If this virtual register is
- // already marked as alive in this basic block, that means it is alive in at
- // least one of the successor blocks, it's not a kill.
- if (!VRInfo.AliveBlocks.test(BBNum))
- VRInfo.Kills.push_back(&MI);
-
- // Update all dominating blocks to mark them as "known live".
- for (MachineBasicBlock *Pred : MBB->predecessors())
- MarkVirtRegAliveInBlock(VRInfo, MRI->getDefBlock(Reg), Pred);
-}
-
-void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
- VarInfo &VRInfo = getVarInfo(Reg);
-
- if (VRInfo.AliveBlocks.empty())
- // If vr is not alive in any block, then defaults to dead.
- VRInfo.Kills.push_back(&MI);
-}
+LiveVariables::LiveVariables(MachineFunction &MF) { analyze(MF); }
/// FindLastPartialDef - Return the last partial def of the specified register.
MachineInstr *LiveVariables::FindLastPartialDef(Register Reg) {
@@ -228,9 +68,6 @@ MachineInstr *LiveVariables::FindLastPartialDef(Register Reg) {
}
}
- if (!LastDef)
- return nullptr;
-
return LastDef;
}
@@ -276,16 +113,11 @@ MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
- unsigned LastPartDefDist = 0;
for (MCPhysReg SubReg : TRI->subregs(Reg)) {
MachineInstr *Def = PhysRegDef[SubReg];
- if (Def && Def != LastDef) {
- // There was a def of this sub-register in between. This is a partial
- // def, keep track of the last one.
- unsigned Dist = DistanceMap[Def];
- if (Dist > LastPartDefDist)
- LastPartDefDist = Dist;
- } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
+ if (Def && Def != LastDef)
+ continue;
+ if (MachineInstr *Use = PhysRegUse[SubReg]) {
unsigned Dist = DistanceMap[Use];
if (Dist > LastRefOrPartRefDist) {
LastRefOrPartRefDist = Dist;
@@ -297,11 +129,11 @@ MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
return LastRefOrPartRef;
}
-bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
+void LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
MachineInstr *LastDef = PhysRegDef[Reg.id()];
MachineInstr *LastUse = PhysRegUse[Reg.id()];
if (!LastDef && !LastUse)
- return false;
+ return;
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
@@ -368,11 +200,7 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
if (NeedDef)
PhysRegDef[Reg.id()]->addOperand(
MachineOperand::CreateReg(SubReg, true /*IsDef*/, true /*IsImp*/));
- MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
- if (LastSubRef)
- LastSubRef->addRegisterKilled(SubReg, TRI, true);
- else {
- LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
+ if (!FindLastRefOrPartRef(SubReg)) {
for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
PhysRegUse[SS] = LastRefOrPartRef;
}
@@ -380,29 +208,21 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
PartUses.erase(SS);
}
} else if (LastRefOrPartRef == PhysRegDef[Reg.id()] &&
- LastRefOrPartRef != MI) {
- if (LastPartDef)
- // The last partial def kills the register.
- LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
- true/*IsImp*/, true/*IsKill*/));
- else {
- MachineOperand *MO =
- LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false);
- bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
- // If the last reference is the last def, then it's not used at all.
- // That is, unless we are currently processing the last reference itself.
- LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
- if (NeedEC) {
- // If we are adding a subreg def and the superreg def is marked early
- // clobber, add an early clobber marker to the subreg def.
- MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr);
- if (MO)
- MO->setIsEarlyClobber();
- }
+ LastRefOrPartRef != MI && !LastPartDef) {
+ MachineOperand *MO =
+ LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false);
+ bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
+ // If the last reference is the last def, then it's not used at all.
+ // That is, unless we are currently processing the last reference itself.
+ LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
+ if (NeedEC) {
+ // If we are adding a subreg def and the superreg def is marked early
+ // clobber, add an early clobber marker to the subreg def.
+ MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr);
+ if (MO)
+ MO->setIsEarlyClobber();
}
- } else
- LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
- return true;
+ }
}
void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) {
@@ -478,62 +298,43 @@ void LiveVariables::runOnInstr(MachineInstr &MI,
SmallVectorImpl<Register> &Defs,
unsigned NumRegs) {
assert(!MI.isDebugOrPseudoInstr());
- // Process all of the operands of the instruction...
- unsigned NumOperandsToProcess = MI.getNumOperands();
- // Unless it is a PHI node. In this case, ONLY process the DEF, not any
- // of the uses. They will be handled in other basic blocks.
- if (MI.isPHI())
- NumOperandsToProcess = 1;
-
- // Clear kill and dead markers. LV will recompute them.
+ // Clear dead markers. LV will recompute them.
SmallVector<Register, 4> UseRegs;
SmallVector<Register, 4> DefRegs;
SmallVector<unsigned, 1> RegMasks;
- for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
- MachineOperand &MO = MI.getOperand(i);
+ for (auto [I, MO] : enumerate(MI.operands())) {
if (MO.isRegMask()) {
- RegMasks.push_back(i);
+ RegMasks.push_back(I);
continue;
}
- if (!MO.isReg() || !MO.getReg())
+ if (!MO.isReg())
continue;
Register MOReg = MO.getReg();
+ if (!MOReg.isPhysical() || MRI->isReserved(MOReg))
+ continue;
if (MO.isUse()) {
- if (!(MOReg.isPhysical() && MRI->isReserved(MOReg)))
- MO.setIsKill(false);
if (MO.readsReg())
UseRegs.push_back(MOReg);
} else {
- assert(MO.isDef());
// FIXME: We should not remove any dead flags. However the MIPS RDDSP
// instruction needs it at the moment: http://llvm.org/PR27116.
- if (MOReg.isPhysical() && !MRI->isReserved(MOReg))
- MO.setIsDead(false);
+ MO.setIsDead(false);
DefRegs.push_back(MOReg);
}
}
- MachineBasicBlock *MBB = MI.getParent();
// Process all uses.
- for (Register MOReg : UseRegs) {
- if (MOReg.isVirtual())
- HandleVirtRegUse(MOReg, MBB, MI);
- else if (!MRI->isReserved(MOReg))
- HandlePhysRegUse(MOReg, MI);
- }
+ for (Register MOReg : UseRegs)
+ HandlePhysRegUse(MOReg, MI);
// Process all masked registers. (Call clobbers).
for (unsigned Mask : RegMasks)
HandleRegMask(MI.getOperand(Mask), NumRegs);
// Process all defs.
- for (Register MOReg : DefRegs) {
- if (MOReg.isVirtual())
- HandleVirtRegDef(MOReg, MI);
- else if (!MRI->isReserved(MOReg))
- HandlePhysRegDef(MOReg, &MI, Defs);
- }
+ for (Register MOReg : DefRegs)
+ HandlePhysRegDef(MOReg, &MI, Defs);
UpdatePhysRegDefs(MI, Defs);
}
@@ -557,18 +358,6 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
runOnInstr(MI, Defs, NumRegs);
}
- // Handle any virtual assignments from PHI nodes which might be at the
- // bottom of this basic block. We check all of our successor blocks to see
- // if they have PHI nodes, and if so, we simulate an assignment at the end
- // of the current block.
- if (!PHIVarInfo[MBB->getNumber()].empty()) {
- SmallVectorImpl<Register> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
-
- for (Register I : VarInfoVec)
- // Mark it alive only in the block we are representing.
- MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getDefBlock(I), MBB);
- }
-
// MachineCSE may CSE instructions which write to non-allocatable physical
// registers across MBBs. Remember if any reserved register is liveout.
SmallSet<MCRegister, 4> LiveOuts;
@@ -590,14 +379,8 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
}
void LiveVariables::analyze(MachineFunction &mf) {
- MF = &mf;
MRI = &mf.getRegInfo();
- TRI = MF->getSubtarget().getRegisterInfo();
-
- const unsigned NumRegs = TRI->getNumSupportedRegs(mf);
- PhysRegDef.assign(NumRegs, nullptr);
- PhysRegUse.assign(NumRegs, nullptr);
- PHIVarInfo.resize(MF->getNumBlockIDs());
+ TRI = mf.getSubtarget().getRegisterInfo();
// FIXME: LiveIntervals will be updated to remove its dependence on
// LiveVariables to improve compilation time and eliminate bizarre pass
@@ -605,274 +388,25 @@ void LiveVariables::analyze(MachineFunction &mf) {
if (!MRI->isSSA())
reportFatalUsageError("regalloc=... not currently supported with -O0");
- analyzePHINodes(mf);
-
- // Calculate live variable information in depth first order on the CFG of the
- // function. This guarantees that we will see the definition of a virtual
- // register before its uses due to dominance properties of SSA (except for PHI
- // nodes, which are treated as a special case).
- MachineBasicBlock *Entry = &MF->front();
- df_iterator_default_set<MachineBasicBlock*,16> Visited;
+ const unsigned NumRegs = TRI->getNumSupportedRegs(mf);
+ PhysRegDef.assign(NumRegs, nullptr);
+ PhysRegUse.assign(NumRegs, nullptr);
- for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
- runOnBlock(MBB, NumRegs);
+ for (MachineBasicBlock &MBB : mf) {
+ runOnBlock(&MBB, NumRegs);
PhysRegDef.assign(NumRegs, nullptr);
PhysRegUse.assign(NumRegs, nullptr);
}
- // Convert and transfer the dead / killed information we have gathered into
- // VirtRegInfo onto MI's.
- for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
- const Register Reg = Register::index2VirtReg(i);
- for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
- if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
- VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
- else
- VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
+ for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ MachineInstr *Def = MRI->getVRegDef(Reg);
+ if (Def && none_of(MRI->use_nodbg_operands(Reg),
+ [](const MachineOperand &MO) { return MO.readsReg(); }))
+ Def->addRegisterDead(Reg, TRI);
}
- // Check to make sure there are no unreachable blocks in the MC CFG for the
- // function. If so, it is due to a bug in the instruction selector or some
- // other part of the code generator if this happens.
-#ifndef NDEBUG
- for (const MachineBasicBlock &MBB : *MF)
- assert(Visited.contains(&MBB) && "unreachable basic block found");
-#endif
-
PhysRegDef.clear();
PhysRegUse.clear();
- PHIVarInfo.clear();
-}
-
-void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
- assert(Reg.isVirtual());
-
- VarInfo &VI = getVarInfo(Reg);
- VI.AliveBlocks.clear();
- VI.Kills.clear();
-
- MachineInstr &DefMI = *MRI->getUniqueVRegDef(Reg);
- MachineBasicBlock &DefBB = *DefMI.getParent();
-
- // Initialize a worklist of BBs that Reg is live-to-end of. (Here
- // "live-to-end" means Reg is live at the end of a block even if it is only
- // live because of phi uses in a successor. This is different from isLiveOut()
- // which does not consider phi uses.)
- SmallVector<MachineBasicBlock *> LiveToEndBlocks;
- SparseBitVector<> UseBlocks;
- unsigned NumRealUses = 0;
- for (auto &UseMO : MRI->use_nodbg_operands(Reg)) {
- UseMO.setIsKill(false);
- if (!UseMO.readsReg())
- continue;
- ++NumRealUses;
- MachineInstr &UseMI = *UseMO.getParent();
- MachineBasicBlock &UseBB = *UseMI.getParent();
- UseBlocks.set(UseBB.getNumber());
- if (UseMI.isPHI()) {
- // If Reg is used in a phi then it is live-to-end of the corresponding
- // predecessor.
- unsigned Idx = UseMO.getOperandNo();
- LiveToEndBlocks.push_back(UseMI.getOperand(Idx + 1).getMBB());
- } else if (&UseBB == &DefBB) {
- // A non-phi use in the same BB as the single def must come after the def.
- } else {
- // Otherwise Reg must be live-to-end of all predecessors.
- LiveToEndBlocks.append(UseBB.pred_begin(), UseBB.pred_end());
- }
- }
-
- // Handle the case where all uses have been removed.
- if (NumRealUses == 0) {
- VI.Kills.push_back(&DefMI);
- DefMI.addRegisterDead(Reg, nullptr);
- return;
- }
- DefMI.clearRegisterDeads(Reg);
-
- // Iterate over the worklist adding blocks to AliveBlocks.
- bool LiveToEndOfDefBB = false;
- while (!LiveToEndBlocks.empty()) {
- MachineBasicBlock &BB = *LiveToEndBlocks.pop_back_val();
- if (&BB == &DefBB) {
- LiveToEndOfDefBB = true;
- continue;
- }
- if (VI.AliveBlocks.test(BB.getNumber()))
- continue;
- VI.AliveBlocks.set(BB.getNumber());
- LiveToEndBlocks.append(BB.pred_begin(), BB.pred_end());
- }
-
- // Recompute kill flags. For each block in which Reg is used but is not
- // live-through, find the last instruction that uses Reg. Ignore phi nodes
- // because they should not be included in Kills.
- for (unsigned UseBBNum : UseBlocks) {
- if (VI.AliveBlocks.test(UseBBNum))
- continue;
- MachineBasicBlock &UseBB = *MF->getBlockNumbered(UseBBNum);
- if (&UseBB == &DefBB && LiveToEndOfDefBB)
- continue;
- for (auto &MI : reverse(UseBB)) {
- if (MI.isDebugOrPseudoInstr())
- continue;
- if (MI.isPHI())
- break;
- if (MI.readsVirtualRegister(Reg)) {
- assert(!MI.killsRegister(Reg, /*TRI=*/nullptr));
- MI.addRegisterKilled(Reg, nullptr);
- VI.Kills.push_back(&MI);
- break;
- }
- }
- }
-}
-
-/// removeVirtualRegistersKilled - Remove all killed info for the specified
-/// instruction.
-void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) {
- for (MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isKill()) {
- MO.setIsKill(false);
- Register Reg = MO.getReg();
- if (Reg.isVirtual()) {
- bool removed = getVarInfo(Reg).removeKill(MI);
- assert(removed && "kill not in register's VarInfo?");
- (void)removed;
- }
- }
- }
-}
-
-/// analyzePHINodes - Gather information about the PHI nodes in here. In
-/// particular, we want to map the variable information of a virtual register
-/// which is used in a PHI node. We map that to the BB the vreg is coming from.
-///
-void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
- for (const auto &MBB : Fn)
- for (const auto &BBI : MBB) {
- if (!BBI.isPHI())
- break;
- for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
- if (BBI.getOperand(i).readsReg())
- PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
- .push_back(BBI.getOperand(i).getReg());
- }
-}
-
-bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
- Register Reg, MachineRegisterInfo &MRI) {
- unsigned Num = MBB.getNumber();
-
- // Reg is live-through.
- if (AliveBlocks.test(Num))
- return true;
-
- // Registers defined in MBB cannot be live in.
- const MachineInstr *Def = MRI.getVRegDef(Reg);
- if (Def && Def->getParent() == &MBB)
- return false;
-
- // Reg was not defined in MBB, was it killed here?
- return findKill(&MBB);
-}
-
-bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) {
- LiveVariables::VarInfo &VI = getVarInfo(Reg);
-
- SmallPtrSet<const MachineBasicBlock *, 8> Kills;
- for (MachineInstr *MI : VI.Kills)
- Kills.insert(MI->getParent());
-
- // Loop over all of the successors of the basic block, checking to see if
- // the value is either live in the block, or if it is killed in the block.
- for (const MachineBasicBlock *SuccMBB : MBB.successors()) {
- // Is it alive in this successor?
- unsigned SuccIdx = SuccMBB->getNumber();
- if (VI.AliveBlocks.test(SuccIdx))
- return true;
- // Or is it live because there is a use in a successor that kills it?
- if (Kills.count(SuccMBB))
- return true;
- }
-
- return false;
-}
-
-/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
-/// variables that are live out of DomBB will be marked as passing live through
-/// BB.
-void LiveVariables::addNewBlock(MachineBasicBlock *BB,
- MachineBasicBlock *DomBB,
- MachineBasicBlock *SuccBB) {
- const unsigned NumNew = BB->getNumber();
-
- DenseSet<Register> Defs, Kills;
-
- MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
- for (; BBI != BBE && BBI->isPHI(); ++BBI) {
- // Record the def of the PHI node.
- Defs.insert(BBI->getOperand(0).getReg());
-
- // All registers used by PHI nodes in SuccBB must be live through BB.
- for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- if (BBI->getOperand(i+1).getMBB() == BB)
- getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
- }
-
- // Record all vreg defs and kills of all instructions in SuccBB.
- for (; BBI != BBE; ++BBI) {
- for (const MachineOperand &Op : BBI->operands()) {
- if (Op.isReg() && Op.getReg().isVirtual()) {
- if (Op.isDef())
- Defs.insert(Op.getReg());
- else if (Op.isKill())
- Kills.insert(Op.getReg());
- }
- }
- }
-
- // Update info for all live variables
- for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
- Register Reg = Register::index2VirtReg(i);
-
- // If the Defs is defined in the successor it can't be live in BB.
- if (Defs.count(Reg))
- continue;
-
- // If the register is either killed in or live through SuccBB it's also live
- // through BB.
- VarInfo &VI = getVarInfo(Reg);
- if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
- VI.AliveBlocks.set(NumNew);
- }
-}
-
-/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
-/// variables that are live out of DomBB will be marked as passing live through
-/// BB. LiveInSets[BB] is *not* updated (because it is not needed during
-/// PHIElimination).
-void LiveVariables::addNewBlock(MachineBasicBlock *BB,
- MachineBasicBlock *DomBB,
- MachineBasicBlock *SuccBB,
- std::vector<SparseBitVector<>> &LiveInSets) {
- const unsigned NumNew = BB->getNumber();
-
- SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()];
- for (unsigned R : BV) {
- Register VirtReg = Register::index2VirtReg(R);
- LiveVariables::VarInfo &VI = getVarInfo(VirtReg);
- VI.AliveBlocks.set(NumNew);
- }
- // All registers used by PHI nodes in SuccBB must be live through BB.
- for (MachineBasicBlock::iterator BBI = SuccBB->begin(),
- BBE = SuccBB->end();
- BBI != BBE && BBI->isPHI(); ++BBI) {
- for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- if (BBI->getOperand(i + 1).getMBB() == BB &&
- BBI->getOperand(i).readsReg())
- getVarInfo(BBI->getOperand(i).getReg())
- .AliveBlocks.set(NumNew);
- }
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index 7bbec99a16bf9..e98fb24a51745 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -14,7 +14,7 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -54,7 +54,7 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -93,7 +93,7 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDAXRW renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i32) from %ir.p)
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -131,7 +131,7 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x8 = LDXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -169,7 +169,7 @@ define i64 @val_compare_and_swap_64_monotonic_seqcst(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -207,7 +207,7 @@ define i64 @val_compare_and_swap_64_release_acquire(ptr %p, i64 %cmp, i64 %new)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x8 = LDAXRX renamable $x0, pcsections !0 :: (volatile load (i64) from %ir.p)
; CHECK-NEXT: $xzr = SUBSXrs renamable $x8, renamable $x1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -874,7 +874,7 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit $nzcv, pcsections !0
; CHECK-NEXT: early-clobber renamable $w10 = STXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -900,7 +900,7 @@ define i8 @atomicrmw_max_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 32, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit $nzcv, pcsections !0
; CHECK-NEXT: early-clobber renamable $w10 = STLXRB killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -928,7 +928,7 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -956,7 +956,7 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -1125,7 +1125,7 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 11, implicit $nzcv, pcsections !0
; CHECK-NEXT: early-clobber renamable $w10 = STXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -1151,7 +1151,7 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = SBFMWri renamable $w8, 0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 40, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w9 = CSELWr renamable $w8, renamable $w1, 12, implicit $nzcv, pcsections !0
; CHECK-NEXT: early-clobber renamable $w10 = STLXRH killed renamable $w9, renamable $x0, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -1179,7 +1179,7 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -1207,7 +1207,7 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (i16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
@@ -1235,7 +1235,7 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (i8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
@@ -1278,7 +1278,7 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (i16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 8, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: Bcc 1, %bb.3, implicit killed $nzcv, pcsections !0
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.4(0x7ffff800), %bb.1(0x00000800)
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-csel.ll b/llvm/test/CodeGen/AArch64/misched-fusion-csel.ll
index 8fa60ee93663d..a0b92ad56a440 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-csel.ll
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-csel.ll
@@ -22,7 +22,7 @@
; CHECK: SU(3): dead $wzr = SUBSWri %0:gpr32common, 13, 0, implicit-def $nzcv
; CHECK: Successors:
; CHECK: SU(4): Ord Latency=0 Cluster
-; CHECK: SU(4): %5:gpr32 = CSELWr %0:gpr32common, %3:gpr32common, 0, implicit killed $nzcv
+; CHECK: SU(4): %5:gpr32 = CSELWr %0:gpr32common, %3:gpr32common, 0, implicit $nzcv
; CHECK: Predecessors:
; CHECK: SU(3): Ord Latency=0 Cluster
; CHECK: SU(5): $w0 = COPY %5:gpr32
@@ -33,7 +33,7 @@
; CHECK: SU(3): dead $xzr = SUBSXri %0:gpr64common, 13, 0, implicit-def $nzcv
; CHECK: Successors:
; CHECK: SU(4): Ord Latency=0 Cluster
-; CHECK: SU(4): %5:gpr64 = CSELXr %0:gpr64common, %3:gpr64common, 0, implicit killed $nzcv
+; CHECK: SU(4): %5:gpr64 = CSELXr %0:gpr64common, %3:gpr64common, 0, implicit $nzcv
; CHECK: Predecessors:
; CHECK: SU(3): Ord Latency=0 Cluster
; CHECK: SU(5): $x0 = COPY %5:gpr64
diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
index 5753f57481c08..53dd8f81a4c76 100644
--- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
+++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
@@ -12,8 +12,8 @@ body: |
; CHECK-NEXT: $sgpr0 = COPY %sval
; CHECK-NEXT: $sgpr1 = COPY %sval
; CHECK-NEXT: $sgpr2 = COPY %sval
- ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: $sgpr3 = COPY %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3
%sval:sreg_32 = S_MOV_B32 0
$sgpr0 = COPY %sval
@@ -35,8 +35,8 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY %vval
; CHECK-NEXT: $vgpr1 = COPY %vval
; CHECK-NEXT: $vgpr2 = COPY %vval
- ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: $vgpr3 = COPY %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
$vgpr0 = COPY %vval
@@ -56,8 +56,8 @@ body: |
; CHECK: %sval:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: $sgpr0 = COPY %sval
; CHECK-NEXT: $sgpr2 = COPY %sval
- ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
- ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: $sgpr3 = COPY %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
+ ; CHECK-NEXT: SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3
%sval:sreg_32 = S_MOV_B32 0
$sgpr0 = COPY %sval
@@ -77,9 +77,9 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY %vval
; CHECK-NEXT: $vgpr1 = COPY %vval
; CHECK-NEXT: $vgpr2 = COPY %vval, implicit-def $vgpr1_vgpr2
- ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: $vgpr3 = COPY %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1_vgpr2
- ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
$vgpr0 = COPY %vval
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
index 960ed7f1a1441..84f125e854c65 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
@@ -27,7 +27,7 @@ define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
; GFX6-SDAG-NEXT: }
; GFX6-SDAG-NEXT: renamable $sgpr0 = S_GETREG_B32 515, implicit $mode
; GFX6-SDAG-NEXT: S_CMP_LG_U32 killed renamable $sgpr0, 0, implicit-def $scc
- ; GFX6-SDAG-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
+ ; GFX6-SDAG-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX6-SDAG-NEXT: {{ $}}
; GFX6-SDAG-NEXT: bb.2:
; GFX6-SDAG-NEXT: S_ENDPGM 0
@@ -52,7 +52,7 @@ define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
; GFX6-GISEL-NEXT: }
; GFX6-GISEL-NEXT: renamable $sgpr0 = S_GETREG_B32 515, implicit $mode
; GFX6-GISEL-NEXT: S_CMP_LG_U32 killed renamable $sgpr0, 0, implicit-def $scc
- ; GFX6-GISEL-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
+ ; GFX6-GISEL-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX6-GISEL-NEXT: {{ $}}
; GFX6-GISEL-NEXT: bb.2:
; GFX6-GISEL-NEXT: S_ENDPGM 0
@@ -107,7 +107,7 @@ define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 {
; GFX6-SDAG-NEXT: }
; GFX6-SDAG-NEXT: renamable $sgpr0 = S_GETREG_B32 515, implicit $mode
; GFX6-SDAG-NEXT: S_CMP_LG_U32 killed renamable $sgpr0, 0, implicit-def $scc
- ; GFX6-SDAG-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
+ ; GFX6-SDAG-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX6-SDAG-NEXT: {{ $}}
; GFX6-SDAG-NEXT: bb.2:
; GFX6-SDAG-NEXT: S_ENDPGM 0
@@ -132,7 +132,7 @@ define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 {
; GFX6-GISEL-NEXT: }
; GFX6-GISEL-NEXT: renamable $sgpr0 = S_GETREG_B32 515, implicit $mode
; GFX6-GISEL-NEXT: S_CMP_LG_U32 killed renamable $sgpr0, 0, implicit-def $scc
- ; GFX6-GISEL-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
+ ; GFX6-GISEL-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GFX6-GISEL-NEXT: {{ $}}
; GFX6-GISEL-NEXT: bb.2:
; GFX6-GISEL-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
index 6b46a7817e1c8..f4c00b5fd3094 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
@@ -79,7 +79,7 @@ body: |
; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc
; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
- ; COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc
+ ; COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
; COALESCE-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec
; COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec
@@ -92,7 +92,7 @@ body: |
; COALESCE-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AV_MOV_]].sub0
; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
- ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+ ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
; COALESCE-NEXT: S_BRANCH %bb.2
; COALESCE-NEXT: {{ $}}
; COALESCE-NEXT: bb.2:
@@ -115,7 +115,7 @@ body: |
; COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec
; COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec
; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
+ ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; COALESCE-NEXT: S_BRANCH %bb.4
; COALESCE-NEXT: {{ $}}
; COALESCE-NEXT: bb.4:
@@ -133,7 +133,7 @@ body: |
; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; GFX908-COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc
; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
- ; GFX908-COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc
+ ; GFX908-COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
; GFX908-COALESCE-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec
; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec
; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec
@@ -146,7 +146,7 @@ body: |
; GFX908-COALESCE-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AV_MOV_]].sub0
; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
- ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+ ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
; GFX908-COALESCE-NEXT: S_BRANCH %bb.2
; GFX908-COALESCE-NEXT: {{ $}}
; GFX908-COALESCE-NEXT: bb.2:
@@ -169,7 +169,7 @@ body: |
; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec
; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec
; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
+ ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
; GFX908-COALESCE-NEXT: S_BRANCH %bb.4
; GFX908-COALESCE-NEXT: {{ $}}
; GFX908-COALESCE-NEXT: bb.4:
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
index f1db16419bfd7..14ce64623402f 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
@@ -62,7 +62,7 @@ body: |
; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
; COALESCE-NEXT: S_BITCMP0_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc
- ; COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc
+ ; COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc
; COALESCE-NEXT: {{ $}}
; COALESCE-NEXT: bb.1:
; COALESCE-NEXT: successors: %bb.3(0x80000000)
@@ -100,7 +100,7 @@ body: |
; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
; GFX908-COALESCE-NEXT: S_BITCMP0_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc
- ; GFX908-COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc
+ ; GFX908-COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc
; GFX908-COALESCE-NEXT: {{ $}}
; GFX908-COALESCE-NEXT: bb.1:
; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000)
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir b/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
index 072b03ac5de05..d14c79df09bfc 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
@@ -14,8 +14,8 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0, $sgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY killed $sgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
; CHECK-NEXT: S_BRANCH %bb.1
@@ -25,26 +25,26 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I32_e64 [[COPY3]], [[COPY1]], implicit $exec
- ; CHECK-NEXT: $vcc = COPY killed [[V_CMP_LT_I32_e64_]]
+ ; CHECK-NEXT: $vcc = COPY [[V_CMP_LT_I32_e64_]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
- ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[COPY3]], [[COPY]], 0, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY3]], [[COPY]], 0, implicit $exec
; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_ADD_U32_e64_]], [[COPY1]], implicit $exec
- ; CHECK-NEXT: $vcc = COPY killed [[V_CMP_EQ_U32_e64_]]
+ ; CHECK-NEXT: $vcc = COPY [[V_CMP_EQ_U32_e64_]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; CHECK-NEXT: $vgpr0 = COPY killed [[COPY5]]
- ; CHECK-NEXT: SI_RETURN implicit killed $vgpr0
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY5]]
+ ; CHECK-NEXT: SI_RETURN implicit $vgpr0
bb.0:
liveins: $vgpr0, $sgpr0
%0:vgpr_32 = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
index d9ab3d15db8b6..820984e5f1705 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
@@ -29,7 +29,7 @@ body: |
# CHECK: bb.3:
# CHECK-NEXT: %2:sreg_32_xm0 = IMPLICIT_DEF
# CHECK-NEXT: %3:sreg_32_xm0 = COPY %4
-# CHECK-NEXT: S_NOP 0, implicit killed %3
+# CHECK-NEXT: S_NOP 0, implicit %3
################################################################################
@@ -67,7 +67,7 @@ body: |
# CHECK: bb.3:
# CHECK-NEXT: %3:sreg_32_xm0 = IMPLICIT_DEF
# CHECK-NEXT: %2:sreg_32_xm0 = COPY %4
-# CHECK-NEXT: S_NOP 0, implicit killed %2
+# CHECK-NEXT: S_NOP 0, implicit %2
# The following test crashes in phi-elimination hooks.
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
index 5c1715dd97452..ffd19ee3b586e 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
@@ -9,7 +9,7 @@
# CHECK: bb.1:
# CHECK: [[END_CF_ARG:%[0-9]+]]:sreg_64 = COPY [[IF_INPUT_REG]]
-# CHECK: SI_END_CF killed [[END_CF_ARG]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK: SI_END_CF [[END_CF_ARG]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
# CHECK: bb.2:
# CHECK: [[IF_SOURCE1:%[0-9]+]]:sreg_64 = SI_IF [[COND]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll b/llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
index cee766b76d35d..db680bc48d999 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
@@ -529,7 +529,7 @@ define amdgpu_kernel void @test_spill_cost_reset(
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_MOV_B32_]], 1, implicit-def dead $scc
; CHECK-NEXT: S_CMP_LT_I32 [[S_MOV_B32_]], [[S_LOAD_DWORD_IMM]], implicit-def $scc
; CHECK-NEXT: [[V_MOV_B32_e32_127:%[0-9]+]]:vreg_64_align2 = nofpexcept V_PK_ADD_F32 8, [[V_MOV_B32_e32_127]], 8, [[V_MOV_B32_e32_127]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.epilogue:
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll b/llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
index fc2af48e69464..281fa591b16e7 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
@@ -19,7 +19,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg
; CHECK-NEXT: $sgpr1 = COPY [[COPY4]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY [[S_LOAD_DWORD_IMM]]
; CHECK-NEXT: $sgpr2 = COPY [[COPY5]]
- ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit killed $sgpr2
+ ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
%load = load <3 x i32>, ptr addrspace(4) %ptr, align 4
ret <3 x i32> %load
}
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
index 7cf711d0c094b..49dc3338e8a1d 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
@@ -169,7 +169,7 @@ define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 {
; SI-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 1, [[PHI6]], 0, implicit $exec
; SI-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[PHI]], 1, implicit-def dead $scc
; SI-NEXT: S_CMP_LT_I32 [[S_ADD_I32_]], [[COPY1]], implicit-def $scc
- ; SI-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
+ ; SI-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; SI-NEXT: S_BRANCH %bb.6
; SI-NEXT: {{ $}}
; SI-NEXT: bb.6.for.end:
@@ -263,7 +263,7 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun
; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]]
; SI-NEXT: $vgpr0 = COPY [[PHI6]]
- ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE1]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
+ ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE1]], 0, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; SI-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 [[PHI4]], $exec_lo, implicit-def dead $scc
@@ -301,7 +301,7 @@ define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_fun
; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY9]]
; SI-NEXT: $vgpr0 = COPY [[PHI9]]
- ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE3]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
+ ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE3]], 0, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; SI-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 [[PHI7]], $exec_lo, implicit-def dead $scc
@@ -386,7 +386,7 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e
; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]]
; SI-NEXT: $vgpr0 = COPY [[COPY4]]
- ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE1]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
+ ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE1]], 0, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; SI-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 [[PHI3]], $exec_lo, implicit-def dead $scc
@@ -423,7 +423,7 @@ define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %e
; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY9]]
; SI-NEXT: $vgpr0 = COPY [[COPY4]]
- ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE3]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
+ ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL [[REG_SEQUENCE3]], 0, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $vgpr0, implicit-def $vgpr0
; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
; SI-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; SI-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 [[PHI5]], $exec_lo, implicit-def dead $scc
diff --git a/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir b/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
index 4f17948630b08..e4fa981744c14 100644
--- a/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
+++ b/llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
@@ -22,12 +22,12 @@ body: |
; W32: successors: %bb.1(0x80000000)
; W32-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; W32-NEXT: {{ $}}
- ; W32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr4
- ; W32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr3
- ; W32-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2
- ; W32-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
- ; W32-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
- ; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, killed [[COPY3]], %subreg.sub1, killed [[COPY2]], %subreg.sub2, killed [[COPY1]], %subreg.sub3
+ ; W32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; W32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; W32-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; W32-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; W32-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY1]], %subreg.sub3
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; W32-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; W32-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[S_MOV_B32_1]]
@@ -42,34 +42,34 @@ body: |
; W32-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub2, implicit $exec
; W32-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub3, implicit $exec
; W32-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
- ; W32-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1, killed [[V_READFIRSTLANE_B32_2]], %subreg.sub2, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; W32-NEXT: V_CMPX_EQ_U64_nosdst_e32_term killed [[REG_SEQUENCE1]], [[REG_SEQUENCE]].sub0_sub1, implicit-def $exec, implicit $exec
- ; W32-NEXT: V_CMPX_EQ_U64_nosdst_e32_term killed [[REG_SEQUENCE2]], [[REG_SEQUENCE]].sub2_sub3, implicit-def $exec, implicit $exec
+ ; W32-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; W32-NEXT: V_CMPX_EQ_U64_nosdst_e32_term [[REG_SEQUENCE1]], [[REG_SEQUENCE]].sub0_sub1, implicit-def $exec, implicit $exec
+ ; W32-NEXT: V_CMPX_EQ_U64_nosdst_e32_term [[REG_SEQUENCE2]], [[REG_SEQUENCE]].sub2_sub3, implicit-def $exec, implicit $exec
; W32-NEXT: {{ $}}
; W32-NEXT: .2:
; W32-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; W32-NEXT: {{ $}}
; W32-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[COPY]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec
- ; W32-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 killed [[COPY6]], $exec_lo, implicit-def dead $scc
+ ; W32-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_ANDN2_B32 [[COPY6]], $exec_lo, implicit-def dead $scc
; W32-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[S_ANDN2_B32_]]
; W32-NEXT: $exec_lo = S_MOV_B32_term [[S_ANDN2_B32_]]
; W32-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; W32-NEXT: {{ $}}
; W32-NEXT: .3:
- ; W32-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_]]
- ; W32-NEXT: $vgpr0 = COPY killed [[BUFFER_LOAD_FORMAT_X_IDXEN]]
- ; W32-NEXT: S_ENDPGM 0, implicit killed $vgpr0
+ ; W32-NEXT: $exec_lo = S_MOV_B32 [[S_MOV_B32_]]
+ ; W32-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_IDXEN]]
+ ; W32-NEXT: S_ENDPGM 0, implicit $vgpr0
;
; W64-LABEL: name: waterfall_exec_update
; W64: successors: %bb.1(0x80000000)
; W64-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; W64-NEXT: {{ $}}
- ; W64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr4
- ; W64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr3
- ; W64-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2
- ; W64-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
- ; W64-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
- ; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, killed [[COPY3]], %subreg.sub1, killed [[COPY2]], %subreg.sub2, killed [[COPY1]], %subreg.sub3
+ ; W64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; W64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+ ; W64-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; W64-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; W64-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY1]], %subreg.sub3
; W64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; W64-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
; W64-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_1]]
@@ -84,23 +84,23 @@ body: |
; W64-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub2, implicit $exec
; W64-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub3, implicit $exec
; W64-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
- ; W64-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1, killed [[V_READFIRSTLANE_B32_2]], %subreg.sub2, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; W64-NEXT: V_CMPX_EQ_U64_nosdst_e32_term killed [[REG_SEQUENCE1]], [[REG_SEQUENCE]].sub0_sub1, implicit-def $exec, implicit $exec
- ; W64-NEXT: V_CMPX_EQ_U64_nosdst_e32_term killed [[REG_SEQUENCE2]], [[REG_SEQUENCE]].sub2_sub3, implicit-def $exec, implicit $exec
+ ; W64-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; W64-NEXT: V_CMPX_EQ_U64_nosdst_e32_term [[REG_SEQUENCE1]], [[REG_SEQUENCE]].sub0_sub1, implicit-def $exec, implicit $exec
+ ; W64-NEXT: V_CMPX_EQ_U64_nosdst_e32_term [[REG_SEQUENCE2]], [[REG_SEQUENCE]].sub2_sub3, implicit-def $exec, implicit $exec
; W64-NEXT: {{ $}}
; W64-NEXT: .2:
; W64-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; W64-NEXT: {{ $}}
; W64-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[COPY]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec
- ; W64-NEXT: [[S_ANDN2_B64_:%[0-9]+]]:sreg_64_xexec = S_ANDN2_B64 killed [[COPY6]], $exec, implicit-def dead $scc
+ ; W64-NEXT: [[S_ANDN2_B64_:%[0-9]+]]:sreg_64_xexec = S_ANDN2_B64 [[COPY6]], $exec, implicit-def dead $scc
; W64-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY [[S_ANDN2_B64_]]
; W64-NEXT: $exec = S_MOV_B64_term [[S_ANDN2_B64_]]
; W64-NEXT: SI_WATERFALL_LOOP %bb.1, implicit $exec
; W64-NEXT: {{ $}}
; W64-NEXT: .3:
- ; W64-NEXT: $exec = S_MOV_B64 killed [[S_MOV_B64_]]
- ; W64-NEXT: $vgpr0 = COPY killed [[BUFFER_LOAD_FORMAT_X_IDXEN]]
- ; W64-NEXT: S_ENDPGM 0, implicit killed $vgpr0
+ ; W64-NEXT: $exec = S_MOV_B64 [[S_MOV_B64_]]
+ ; W64-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_IDXEN]]
+ ; W64-NEXT: S_ENDPGM 0, implicit $vgpr0
%4:vgpr_32 = COPY $vgpr4
%3:vgpr_32 = COPY $vgpr3
%2:vgpr_32 = COPY $vgpr2
diff --git a/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir b/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
index 01707e1d326d8..20080b35a3525 100644
--- a/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
+++ b/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
@@ -64,7 +64,7 @@ body: |
#
# CHECK: bb.0:
# CHECK: %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51
-# CHECK-NEXT: %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit killed $x2 :: (load (s64))
+# CHECK-NEXT: %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit $x2 :: (load (s64))
# CHECK-NEXT: %2:gprc = LI 0
# CHECK-NEXT: %3:crrc = CMPLWI killed %2, 0
# CHECK-NEXT: BCC 76, killed %3, %bb.2
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index 176199bd3b3ab..6ef66ab0d4bc9 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -13,7 +13,7 @@ define void @call_test_chars() {
; 32BIT-NEXT: $r4 = LI 97
; 32BIT-NEXT: $r5 = LI 97
; 32BIT-NEXT: $r6 = LI 97
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -24,7 +24,7 @@ define void @call_test_chars() {
; 64BIT-NEXT: $x4 = LI8 97
; 64BIT-NEXT: $x5 = LI8 97
; 64BIT-NEXT: $x6 = LI8 97
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_chars>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_chars>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -72,7 +72,7 @@ define void @call_test_chars_mix() {
; 32BIT-NEXT: $r4 = LI 225
; 32BIT-NEXT: $r5 = LI 97
; 32BIT-NEXT: $r6 = LI -31
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_chars_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_chars_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -83,7 +83,7 @@ define void @call_test_chars_mix() {
; 64BIT-NEXT: $x4 = LI8 225
; 64BIT-NEXT: $x5 = LI8 97
; 64BIT-NEXT: $x6 = LI8 -31
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_chars_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_chars_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -154,7 +154,7 @@ define void @call_test_i1() {
; 32BIT: bb.0.entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 1
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_i1>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_i1>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -162,7 +162,7 @@ define void @call_test_i1() {
; 64BIT: bb.0.entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 1
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i1>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i1>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -241,7 +241,7 @@ define void @call_test_ints() {
; 32BIT-NEXT: $r8 = LI 1
; 32BIT-NEXT: $r9 = LI 1
; 32BIT-NEXT: $r10 = LI 1
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_ints>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_ints>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -257,7 +257,7 @@ define void @call_test_ints() {
; 64BIT-NEXT: $x8 = LI8 1
; 64BIT-NEXT: $x9 = LI8 1
; 64BIT-NEXT: $x10 = LI8 1
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_ints>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_ints>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -277,7 +277,7 @@ define void @call_test_i64() {
; 32BIT-NEXT: $r8 = LI 3
; 32BIT-NEXT: $r9 = LI 0
; 32BIT-NEXT: $r10 = LI 4
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_i64>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3, implicit-def dead $r4
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_i64>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3, implicit-def dead $r4
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -288,7 +288,7 @@ define void @call_test_i64() {
; 64BIT-NEXT: $x4 = LI8 2
; 64BIT-NEXT: $x5 = LI8 3
; 64BIT-NEXT: $x6 = LI8 4
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i64>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_i64>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -302,11 +302,11 @@ define i64 @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) {
; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
; 32BIT-NEXT: {{ $}}
; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r6, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r5, implicit-def dead $carry, implicit killed $carry
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r5, implicit-def dead $carry, implicit $carry
; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r8, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r7, implicit-def dead $carry, implicit killed $carry
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r7, implicit-def dead $carry, implicit $carry
; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r4, killed renamable $r10, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r9, implicit-def dead $carry, implicit killed $carry
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r3, killed renamable $r9, implicit-def dead $carry, implicit $carry
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
;
; 64BIT-LABEL: name: test_i64
@@ -426,7 +426,7 @@ define void @call_test_floats() {
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $f2 = COPY renamable $f1
; 32BIT-NEXT: $f3 = COPY renamable $f1
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $r2, implicit-def $r1, implicit-def dead $f1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $r2, implicit-def $r1, implicit-def dead $f1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -437,7 +437,7 @@ define void @call_test_floats() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $f2 = COPY renamable $f1
; 64BIT-NEXT: $f3 = COPY renamable $f1
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_floats>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1, implicit-def dead $f1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_floats>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $x2, implicit-def $r1, implicit-def dead $f1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -495,7 +495,7 @@ define void @call_test_fpr_max() {
; 32BIT-NEXT: $f12 = COPY renamable $f1
; 32BIT-NEXT: $f13 = COPY renamable $f1
; 32BIT-NEXT: STFD renamable $f1, 56, $r1 :: (store (s64) into stack + 56, basealign 16)
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
; 32BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -521,7 +521,7 @@ define void @call_test_fpr_max() {
; 64BIT-NEXT: $f12 = COPY renamable $f1
; 64BIT-NEXT: $f13 = COPY renamable $f1
; 64BIT-NEXT: STFD renamable $f1, 112, $x1 :: (store (s64) into stack + 112, align 16)
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -592,7 +592,7 @@ define void @call_test_mix() {
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r4 = LI 1
; 32BIT-NEXT: $r7 = LI 97
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit killed $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -605,7 +605,7 @@ define void @call_test_mix() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x4 = LI8 1
; 64BIT-NEXT: $x6 = LI8 97
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -680,7 +680,7 @@ define i64 @callee_mixed_ints(i32 %a, i8 signext %b, i32 %c, i16 signext %d, i64
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
; 32BIT-NEXT: renamable $r5 = SRAWI renamable $r3, 31, implicit-def dead $carry
; 32BIT-NEXT: renamable $r4 = ADDC killed renamable $r3, killed renamable $r8, implicit-def $carry
- ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r5, killed renamable $r7, implicit-def dead $carry, implicit killed $carry
+ ; 32BIT-NEXT: renamable $r3 = ADDE killed renamable $r5, killed renamable $r7, implicit-def dead $carry, implicit $carry
; 32BIT-NEXT: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
;
; 64BIT-LABEL: name: callee_mixed_ints
@@ -765,7 +765,7 @@ define void @call_test_vararg2() {
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 42
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -782,7 +782,7 @@ define void @call_test_vararg2() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -810,7 +810,7 @@ define void @call_test_vararg3() {
; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 0
; 32BIT-NEXT: $r7 = LI 42
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -827,7 +827,7 @@ define void @call_test_vararg3() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -966,7 +966,7 @@ define void @call_test_stackarg_float() {
; 32BIT-NEXT: $r9 = LI 7
; 32BIT-NEXT: $r10 = LI 8
; 32BIT-NEXT: STFS renamable $f1, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -987,7 +987,7 @@ define void @call_test_stackarg_float() {
; 64BIT-NEXT: $x9 = LI8 7
; 64BIT-NEXT: $x10 = LI8 8
; 64BIT-NEXT: STFS renamable $f1, 112, $x1 :: (store (s32) into stack + 112, align 16)
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -1014,7 +1014,7 @@ define void @call_test_stackarg_float2() {
; 32BIT-NEXT: $r6 = LI 4
; 32BIT-NEXT: $r7 = LI 5
; 32BIT-NEXT: $r8 = LI 6
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -1031,7 +1031,7 @@ define void @call_test_stackarg_float2() {
; 64BIT-NEXT: $x6 = LI8 4
; 64BIT-NEXT: $x7 = LI8 5
; 64BIT-NEXT: $x8 = LI8 6
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -1062,7 +1062,7 @@ define void @call_test_stackarg_float3() {
; 32BIT-NEXT: $r8 = LI 6
; 32BIT-NEXT: $r9 = LI 7
; 32BIT-NEXT: STFD renamable $f1, 52, $r1 :: (store (s64) into stack + 52, align 4, basealign 16)
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -1083,7 +1083,7 @@ define void @call_test_stackarg_float3() {
; 64BIT-NEXT: $x8 = LI8 6
; 64BIT-NEXT: $x9 = LI8 7
; 64BIT-NEXT: STFS renamable $f2, 112, $x1 :: (store (s32) into stack + 112, align 16)
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -1149,7 +1149,7 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 64BIT-NEXT: renamable $x2 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0)
; 64BIT-NEXT: renamable $x31 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
; 64BIT-NEXT: renamable $x30 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
- ; 64BIT-NEXT: renamable $x29 = LHA8 2, %fixed-stack.6
+ ; 64BIT-NEXT: renamable $x29 = LHA8 2, %fixed-stack.6 :: (load (s16) from %fixed-stack.6 + 2, basealign 4)
; 64BIT-NEXT: renamable $x28 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16)
; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
@@ -1523,7 +1523,7 @@ define void @caller_fpr_stack() {
; 32BIT-NEXT: STFD killed renamable $f0, 132, $r1 :: (store (s64) into stack + 132, align 4, basealign 16)
; 32BIT-NEXT: $f10 = COPY renamable $f1
; 32BIT-NEXT: STW killed renamable $r3, 128, $r1 :: (store (s32) into stack + 128, align 16)
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
; 32BIT-NEXT: ADJCALLSTACKUP 144, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -1594,7 +1594,7 @@ define void @caller_fpr_stack() {
; 64BIT-NEXT: STD killed renamable $x4, 128, $x1 :: (store (s64) into stack + 128, align 16)
; 64BIT-NEXT: STD killed renamable $x7, 120, $x1 :: (store (s64) into stack + 120, basealign 16)
; 64BIT-NEXT: STD killed renamable $x8, 112, $x1 :: (store (s64) into stack + 112, align 16)
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -1734,7 +1734,7 @@ define void @caller_mix() {
; 64BIT-NEXT: $x10 = LI8 40
; 64BIT-NEXT: STD killed renamable $x4, 120, $x1 :: (store (s64) into stack + 120, basealign 16)
; 64BIT-NEXT: STD killed renamable $x5, 112, $x1 :: (store (s64) into stack + 112, align 16)
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .mix_callee>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit killed $x7, implicit killed $x8, implicit $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .mix_callee>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
index 162ffc9e1df2b..6e888e9ebf93b 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
@@ -79,7 +79,7 @@ define void @call_test_byval_2Byte() {
; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $f2 = COPY renamable $f1
; 32BIT-NEXT: $r7 = LI 43
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit killed $f2, implicit killed $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit $f2, implicit $r7, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -94,7 +94,7 @@ define void @call_test_byval_2Byte() {
; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $f2 = COPY renamable $f1
; 64BIT-NEXT: $x7 = LI8 43
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit $f2, implicit $x7, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
@@ -146,7 +146,7 @@ define void @call_test_byval_3Byte() {
; 32BIT-NEXT: $r7 = LI 5
; 32BIT-NEXT: $r8 = LI 6
; 32BIT-NEXT: $r9 = LI 7
- ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_3Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
+ ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_3Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: BLR implicit $lr, implicit $rm
;
@@ -167,7 +167,7 @@ define void @call_test_byval_3Byte() {
; 64BIT-NEXT: $x7 = LI8 5
; 64BIT-NEXT: $x8 = LI8 6
; 64BIT-NEXT: $x9 = LI8 7
- ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_3Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_3Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
entry:
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
index 9b1893b111556..fd421b48e1f63 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
@@ -46,7 +46,7 @@ entry:
; CHECK32-DAG: STW renamable $r8, 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20
; CHECK32-DAG: STW killed renamable $r9, 24, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 24
; CHECK32: renamable $r4 = ADDC killed renamable $r8, killed renamable $r[[REG2]], implicit-def $carry
-; CHECK32: renamable $r3 = ADDE killed renamable $r7, killed renamable $r[[REG1]], implicit-def dead $carry, implicit killed $carry
+; CHECK32: renamable $r3 = ADDE killed renamable $r7, killed renamable $r[[REG1]], implicit-def dead $carry, implicit $carry
; CHECK32 STW killed renamable $r10, 28, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 28
; CHECK32: BLR implicit $lr, implicit $rm, implicit $r3, implicit $r4
diff --git a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
index 83e189f086f15..19c98ea99b129 100644
--- a/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
@@ -72,7 +72,7 @@ define double @caller() {
; MIR32-NEXT: $f11 = XXLXORdpz
; MIR32-NEXT: $f12 = XXLXORdpz
; MIR32-NEXT: $f13 = XXLXORdpz
- ; MIR32-NEXT: BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $f1, implicit killed $f2, implicit killed $v2, implicit killed $v3, implicit killed $v4, implicit killed $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def $f1
+ ; MIR32-NEXT: BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $f1, implicit $f2, implicit $v2, implicit $v3, implicit $v4, implicit $v5, implicit $v6, implicit $v7, implicit $v8, implicit $v9, implicit $v10, implicit $v11, implicit $v12, implicit $v13, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def $f1
; MIR32-NEXT: ADJCALLSTACKUP 188, 0, implicit-def dead $r1, implicit $r1
; MIR32-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
;
@@ -131,7 +131,7 @@ define double @caller() {
; MIR64-NEXT: $f11 = XXLXORdpz
; MIR64-NEXT: $f12 = XXLXORdpz
; MIR64-NEXT: $f13 = XXLXORdpz
- ; MIR64-NEXT: BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $f1, implicit killed $f2, implicit killed $v2, implicit killed $v3, implicit killed $v4, implicit killed $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1, implicit-def $f1
+ ; MIR64-NEXT: BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $f1, implicit $f2, implicit $v2, implicit $v3, implicit $v4, implicit $v5, implicit $v6, implicit $v7, implicit $v8, implicit $v9, implicit $v10, implicit $v11, implicit $v12, implicit $v13, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def $f1
; MIR64-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1
; MIR64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
entry:
diff --git a/llvm/test/CodeGen/PowerPC/mflr-store.mir b/llvm/test/CodeGen/PowerPC/mflr-store.mir
index 460b13ef9fb20..ef348ab455bbd 100644
--- a/llvm/test/CodeGen/PowerPC/mflr-store.mir
+++ b/llvm/test/CodeGen/PowerPC/mflr-store.mir
@@ -31,7 +31,7 @@ body: |
; CHECK-NEXT: $x1 = ADDI8 $x1, 32752
; CHECK-NEXT: $x0 = LD 16, $x1
; CHECK-NEXT: MTLR8 $x0, implicit-def $lr8
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
BL8 @test_callee, csr_ppc64_r2, implicit-def dead $lr8, implicit $rm, implicit-def $r1, implicit-def $x3
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
diff --git a/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir b/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
index 3ee857b7b1b18..79de2d1281797 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
- ; CHECK-NEXT: BRC 14, 6, %bb.2, implicit killed $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.2, implicit $cc
; CHECK-NEXT: J %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/X86/AMX/amx-greedy-ra.ll b/llvm/test/CodeGen/X86/AMX/amx-greedy-ra.ll
index 23a389d4b1202..161121f01e8b1 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-greedy-ra.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-greedy-ra.ll
@@ -26,7 +26,7 @@ define i16 @foo(i32 noundef %t, i16 %row, i16 %col) nounwind {
; CHECK-NEXT: dead [[PTILEZEROV2:%[0-9]+]]:tile = PTDPBSSDV [[COPY1]].sub_16bit, [[COPY]].sub_16bit, [[COPY]].sub_16bit, [[PTILEZEROV2]], [[PTILEZEROV]], [[PTILEZEROV1]]
; CHECK-NEXT: [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r [[COPY1]], 1, [[COPY]], 0, $noreg
; CHECK-NEXT: $ax = COPY [[LEA64_32r]].sub_16bit
- ; CHECK-NEXT: RET 0, killed $ax
+ ; CHECK-NEXT: RET 0, $ax
entry:
%0 = tail call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 %col)
%1 = tail call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 %col)
diff --git a/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll b/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
index aa2694f05e2e3..612913f1a6fe2 100644
--- a/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
+++ b/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
@@ -15,7 +15,7 @@ define i32 @foo(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m) #0 {
; PEI-LABEL: name: foo
; PEI: $ebp = frame-destroy POP32r implicit-def $esp, implicit $esp
; PEI-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $esp, 4
-; PEI-NEXT: RET 0, killed $eax
+; PEI-NEXT: RET 0, $eax
entry:
%i.addr = alloca i32, align 4
diff --git a/llvm/test/CodeGen/X86/live-vars.ll b/llvm/test/CodeGen/X86/live-vars.ll
deleted file mode 100644
index aa2448989059b..0000000000000
--- a/llvm/test/CodeGen/X86/live-vars.ll
+++ /dev/null
@@ -1,27 +0,0 @@
-; RUN: llc -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel %s -o - | llc -passes='print<live-vars>' -x mir 2>&1 | FileCheck %s
-
-define i32 @foo(i32 noundef %0) local_unnamed_addr {
- %2 = icmp eq i32 %0, 0
- br i1 %2, label %13, label %3
-
-3: ; preds = %1
- %4 = add i32 %0, -1
- %5 = zext i32 %4 to i33
- %6 = add i32 %0, -2
- %7 = zext i32 %6 to i33
- %8 = mul i33 %5, %7
- %9 = lshr i33 %8, 1
- %10 = trunc i33 %9 to i32
- %11 = add i32 %10, %0
- %12 = add i32 %11, -1
- br label %13
-
-13: ; preds = %3, %1
- %14 = phi i32 [ 0, %1 ], [ %12, %3 ]
- ret i32 %14
-}
-
-; CHECK: Live variables in machine function: foo
-; CHECK: Virtual register '%0':
-; CHECK: Alive in blocks:
-; CHECK: Killed by: No instructions.
diff --git a/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll b/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll
index ec67467d07014..e477b76cf795d 100644
--- a/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll
+++ b/llvm/test/CodeGen/X86/lvi-hardening-gadget-graph.ll
@@ -70,7 +70,7 @@ for.end: ; preds = %for.cond
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
-; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.6, 13, implicit killed $eflags\n}"];
+; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.6, 13, implicit $eflags\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{CMP32rm killed renamable $eax, %stack.2.secret_size.addr, 1, $noreg, 0, $noreg, implicit-def $eflags :: (dereferenceable load (s32) from %ir.secret_size.addr)\n}"];
@@ -79,7 +79,7 @@ for.end: ; preds = %for.cond
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $eax = MOV32rm %stack.4.i, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.i)\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[color = red, style = "dashed"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
-; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.4, 5, implicit killed $eflags\n}"];
+; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{JCC_1 %bb.4, 5, implicit $eflags\n}"];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} -> Node0x{{[0-9a-f]+}}[label = 1];
; CHECK-NEXT: Node0x{{[0-9a-f]+}} [shape=record,label="{renamable $rax = MOV64rm %stack.1.secret.addr, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.secret.addr)\n}"];
diff --git a/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir b/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
index c8d25f2cb618f..7901432a2bd8d 100644
--- a/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
+++ b/llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
@@ -17,8 +17,8 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
- ; CHECK-NEXT: TEST32rr killed [[MOV32r0_]], [[MOV32r0_]], implicit-def $eflags
- ; CHECK-NEXT: JCC_1 %bb.4, 4, implicit killed $eflags
+ ; CHECK-NEXT: TEST32rr [[MOV32r0_]], [[MOV32r0_]], implicit-def $eflags
+ ; CHECK-NEXT: JCC_1 %bb.4, 4, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -34,8 +34,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[DEF]]
- ; CHECK-NEXT: $xmm0 = COPY killed [[COPY]]
- ; CHECK-NEXT: RET 0, implicit killed $xmm0
+ ; CHECK-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $xmm0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.3(0x80000000)
diff --git a/llvm/test/CodeGen/X86/pr58914.mir b/llvm/test/CodeGen/X86/pr58914.mir
index ff97dda1198c5..acfd541194186 100644
--- a/llvm/test/CodeGen/X86/pr58914.mir
+++ b/llvm/test/CodeGen/X86/pr58914.mir
@@ -12,15 +12,15 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $rcx, $ymm0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_nosp = COPY killed $rcx
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256x = COPY killed $ymm0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_nosp = COPY $rcx
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vk16wm = COPY $rsp
; CHECK-NEXT: [[VBLENDMPDZ256rmk:%[0-9]+]]:vr256x = VBLENDMPDZ256rmk killed [[COPY2]], [[COPY1]], %stack.0, 8, [[COPY]], 0, $noreg
- ; CHECK-NEXT: RET killed [[VBLENDMPDZ256rmk]]
+ ; CHECK-NEXT: RET [[VBLENDMPDZ256rmk]]
bb.0:
successors: %bb.1(0x7c000000)
liveins: $rcx, $ymm0
diff --git a/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll b/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
index c44eaef287611..0552bb9458ac6 100644
--- a/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
+++ b/llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
@@ -22,7 +22,7 @@ define void @test(ptr addrspace(1) %a) gc "statepoint-example" {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = STATEPOINT 2, 5, 0, undef %2:gr64, 2, 0, 2, 0, 2, 0, 2, 1, [[COPY1]](tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: TEST64rr [[COPY]], [[COPY]], implicit-def $eflags
- ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.not_zero:
@@ -67,7 +67,7 @@ define void @test2(ptr addrspace(1) %this, i32 %0, ptr addrspace(1) %p0, ptr add
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY [[COPY3]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr64 = COPY [[COPY2]]
; CHECK-NEXT: TEST64rr [[COPY5]], [[COPY5]], implicit-def $eflags
- ; CHECK-NEXT: JCC_1 %bb.6, 5, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.6, 5, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.BB3:
@@ -89,7 +89,7 @@ define void @test2(ptr addrspace(1) %this, i32 %0, ptr addrspace(1) %p0, ptr add
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gr8 = COPY [[MOV32r0_]].sub_8bit
; CHECK-NEXT: TEST8rr [[COPY7]], [[COPY7]], implicit-def $eflags
- ; CHECK-NEXT: JCC_1 %bb.5, 5, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.5, 5, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.BB4:
@@ -104,7 +104,7 @@ define void @test2(ptr addrspace(1) %this, i32 %0, ptr addrspace(1) %p0, ptr add
; CHECK-NEXT: TEST64rr [[COPY4]], [[COPY4]], implicit-def $eflags
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY9]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY8]]
- ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.BB1:
diff --git a/llvm/test/CodeGen/X86/statepoint-ra.ll b/llvm/test/CodeGen/X86/statepoint-ra.ll
index 8a3a9f2c4edbf..887a18afff340 100644
--- a/llvm/test/CodeGen/X86/statepoint-ra.ll
+++ b/llvm/test/CodeGen/X86/statepoint-ra.ll
@@ -88,7 +88,7 @@ declare token @llvm.experimental.gc.statepoint.p0(i64 , i32 , ptr, i32 , i32 , .
;CHECK: MOVSDmr %stack.2, 1, $noreg, 0, $noreg, %52 :: (store (s64) into %stack.2)
;CHECK: MOVSDmr %stack.5, 1, $noreg, 0, $noreg, %64 :: (store (s64) into %stack.5)
;CHECK: MOVSDmr %stack.6, 1, $noreg, 0, $noreg, %68 :: (store (s64) into %stack.6)
-;CHECK: JCC_1 %bb.2, 4, implicit killed $eflags
+;CHECK: JCC_1 %bb.2, 4, implicit $eflags
;CHECK: bb.1:
;CHECK: successors: %bb.3(0x80000000)
;CHECK: %60:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s64) from constant-pool)
@@ -118,7 +118,7 @@ declare token @llvm.experimental.gc.statepoint.p0(i64 , i32 , ptr, i32 , i32 , .
;CHECK: successors: %bb.7(0x7ffff800), %bb.4(0x00000800)
;CHECK: %24:gr32 = MOV32r0 implicit-def dead $eflags
;CHECK: TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
-;CHECK: JCC_1 %bb.7, 5, implicit killed $eflags
+;CHECK: JCC_1 %bb.7, 5, implicit $eflags
;CHECK: JMP_1 %bb.4
;CHECK: bb.4.bb19:
;CHECK: successors: %bb.5(0x00000000), %bb.6(0x80000000)
@@ -145,7 +145,7 @@ declare token @llvm.experimental.gc.statepoint.p0(i64 , i32 , ptr, i32 , i32 , .
;CHECK: $esi = MOV32ri 51
;CHECK: %75:fr64 = MOVSDrm_alt %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.2)
;CHECK: $xmm7 = COPY %75
-;CHECK: STATEPOINT 2, 5, 10, undef %36:gr64, undef $rdi, $xmm0, $xmm1, $xmm2, $xmm3, $xmm4, $xmm5, $xmm6, $xmm7, killed $esi, 2, 0, 2, 0, 2, 105, 2, 0, 2, 2, 2, 0, 2, 97, 2, 0, 2, 26, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 2, 2, 2, 2, 46, 2, 0, 2, 20, 2, 0, 2, 0, 2, 4278124286, 2, 4, 1, 8, %stack.6, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.5, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.4, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.2, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.3, 0, 2, 7, 2, 0, 2, 4, 1, 8, %fixed-stack.3, 0, 2, 7, 2, 0, 2, 4, 1, 8, %fixed-stack.2, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.7, 0, 2, 7, 2, 0, 2, 3, 2, 51, 2, 1, 2, 4278124286, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp :: (load (s64) from %stack.1), (load (s64) from %stack.2), (load (s64) from %stack.3), (load (s64) from %stack.4), (load (s64) from %stack.5), (load (s64) from %stack.6), (load (s64) from %fixed-stack.2), (load (s64) from %fixed-stack.3, align 16), (load (s64) from %stack.7)
+;CHECK: STATEPOINT 2, 5, 10, undef %36:gr64, undef $rdi, $xmm0, $xmm1, $xmm2, $xmm3, $xmm4, $xmm5, $xmm6, $xmm7, $esi, 2, 0, 2, 0, 2, 105, 2, 0, 2, 2, 2, 0, 2, 97, 2, 0, 2, 26, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 2, 2, 2, 2, 46, 2, 0, 2, 20, 2, 0, 2, 0, 2, 4278124286, 2, 4, 1, 8, %stack.6, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.5, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.4, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.2, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.1, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.3, 0, 2, 7, 2, 0, 2, 4, 1, 8, %fixed-stack.3, 0, 2, 7, 2, 0, 2, 4, 1, 8, %fixed-stack.2, 0, 2, 7, 2, 0, 2, 4, 1, 8, %stack.7, 0, 2, 7, 2, 0, 2, 3, 2, 51, 2, 1, 2, 4278124286, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp :: (load (s64) from %stack.1), (load (s64) from %stack.2), (load (s64) from %stack.3), (load (s64) from %stack.4), (load (s64) from %stack.5), (load (s64) from %stack.6), (load (s64) from %fixed-stack.2), (load (s64) from %fixed-stack.3, align 16), (load (s64) from %stack.7)
;CHECK: ADJCALLSTACKUP64 8, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
;CHECK: bb.6.bb23 (landing-pad):
;CHECK: liveins: $rax, $rdx
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
index 5524a38918b14..9f3de90b0b6ec 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
@@ -70,7 +70,7 @@ define ptr addrspace(1) @test_invoke_same_val(i1 %cond, ptr addrspace(1) %val1,
; CHECK-NEXT: renamable $r15 = COPY $rdx
; CHECK-NEXT: renamable $ebx = COPY $edi
; CHECK-NEXT: TEST8ri renamable $bl, 1, implicit-def $eflags
- ; CHECK-NEXT: JCC_1 %bb.3, 4, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.left:
@@ -116,7 +116,7 @@ define ptr addrspace(1) @test_invoke_same_val(i1 %cond, ptr addrspace(1) %val1,
; CHECK-NEXT: liveins: $ebx, $r14, $r15
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: TEST8ri renamable $bl, 1, implicit-def $eflags, implicit killed $ebx
- ; CHECK-NEXT: renamable $r14 = CMOV64rr killed renamable $r14, killed renamable $r15, 4, implicit killed $eflags
+ ; CHECK-NEXT: renamable $r14 = CMOV64rr killed renamable $r14, killed renamable $r15, 4, implicit $eflags
; CHECK-NEXT: $rax = COPY killed renamable $r14
; CHECK-NEXT: RET 0, $rax
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll b/llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
index 65f5d65cb746c..c40e419089ea0 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
@@ -52,7 +52,7 @@ define i32 @test_spill(
; CHECK-VREG-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = ADD32rm [[MOV32rm]], [[MOV64rm10]], 1, $noreg, 68, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep16, addrspace 1)
; CHECK-VREG-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = ADD32rm [[MOV32rm]], [[MOV64rm11]], 1, $noreg, 72, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep17, addrspace 1)
; CHECK-VREG-NEXT: $eax = COPY [[MOV32rm]]
- ; CHECK-VREG-NEXT: RET 0, killed $eax
+ ; CHECK-VREG-NEXT: RET 0, $eax
;
; CHECK-PREG-LABEL: name: test_spill
; CHECK-PREG: bb.0 (%ir-block.0):
diff --git a/llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir b/llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
index fb6411f8ab2f8..41dd9218b89d1 100644
--- a/llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
+++ b/llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
@@ -23,7 +23,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY killed $rdi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY killed $esi
- ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm killed [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
+ ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV32rm]]
; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gr32 = IMUL32rr [[COPY2]], [[COPY1]], implicit-def dead $eflags
; CHECK-NEXT: dead $rax = SUBREG_TO_REG killed [[COPY1]], %subreg.sub_32bit
@@ -56,7 +56,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY killed $rdi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY killed $esi
- ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm killed [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
+ ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV32rm]]
; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gr32 = IMUL32rr [[COPY2]], [[COPY1]], implicit-def dead $eflags
; CHECK-NEXT: dead [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[COPY1]], %subreg.sub_32bit
@@ -87,7 +87,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY killed $rdi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY killed $esi
- ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm killed [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
+ ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV32rm]]
; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gr32 = IMUL32rr [[COPY2]], [[COPY1]], implicit-def dead $eflags
; CHECK-NEXT: dead $eax = COPY killed [[COPY1]]
@@ -119,7 +119,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY killed $rdi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY killed $esi
- ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm killed [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
+ ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 4, $noreg :: (load (s32) from `ptr undef`)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV32rm]]
; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:gr32 = IMUL32rr [[COPY2]], [[COPY1]], implicit-def dead $eflags
; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:gr32 = COPY killed [[COPY1]]
diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp
index 28cb59b1dd478..25388e4d41556 100644
--- a/llvm/unittests/MI/LiveIntervalTest.cpp
+++ b/llvm/unittests/MI/LiveIntervalTest.cpp
@@ -1,6 +1,5 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -237,23 +236,6 @@ body: |
doTest<LiveIntervalsWrapperPass>(MIRString, T, ShouldPass);
}
-static void liveVariablesTest(StringRef MIRFunc,
- TestPassT<LiveVariablesWrapperPass>::TestFx T,
- bool ShouldPass = true) {
- SmallString<160> S;
- StringRef MIRString = (Twine(R"MIR(
----
-...
-name: func
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
-body: |
- bb.0:
-)MIR") + Twine(MIRFunc) + Twine("...\n")).toNullTerminatedStringRef(S);
- doTest<LiveVariablesWrapperPass>(MIRString, T, ShouldPass);
-}
-
} // End of anonymous namespace.
char TestPass::ID = 0;
@@ -917,52 +899,6 @@ TEST(LiveIntervalTest, LiveThroughSegments) {
false);
}
-TEST(LiveVariablesTest, recomputeForSingleDefVirtReg_handle_undef1) {
- liveVariablesTest(
- R"MIR(
- %0 = IMPLICIT_DEF
- S_NOP 0, implicit %0
- S_NOP 0, implicit undef %0
-)MIR",
- [](MachineFunction &MF, LiveVariablesWrapperPass &LVWrapper) {
- auto &LV = LVWrapper.getLV();
- auto &FirstNop = getMI(MF, 1, 0);
- auto &SecondNop = getMI(MF, 2, 0);
- EXPECT_TRUE(FirstNop.getOperand(1).isKill());
- EXPECT_FALSE(SecondNop.getOperand(1).isKill());
-
- Register R = Register::index2VirtReg(0);
- LV.recomputeForSingleDefVirtReg(R);
-
- EXPECT_TRUE(FirstNop.getOperand(1).isKill());
- EXPECT_FALSE(SecondNop.getOperand(1).isKill());
- });
-}
-
-TEST(LiveVariablesTest, recomputeForSingleDefVirtReg_handle_undef2) {
- liveVariablesTest(
- R"MIR(
- %0 = IMPLICIT_DEF
- S_NOP 0, implicit %0
- S_NOP 0, implicit undef %0, implicit %0
-)MIR",
- [](MachineFunction &MF, LiveVariablesWrapperPass &LVWrapper) {
- auto &LV = LVWrapper.getLV();
- auto &FirstNop = getMI(MF, 1, 0);
- auto &SecondNop = getMI(MF, 2, 0);
- EXPECT_FALSE(FirstNop.getOperand(1).isKill());
- EXPECT_FALSE(SecondNop.getOperand(1).isKill());
- EXPECT_TRUE(SecondNop.getOperand(2).isKill());
-
- Register R = Register::index2VirtReg(0);
- LV.recomputeForSingleDefVirtReg(R);
-
- EXPECT_FALSE(FirstNop.getOperand(1).isKill());
- EXPECT_FALSE(SecondNop.getOperand(1).isKill());
- EXPECT_TRUE(SecondNop.getOperand(2).isKill());
- });
-}
-
int main(int argc, char **argv) {
::testing::InitGoogleTest(&argc, argv);
initLLVM();
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