[llvm-branch-commits] [llvm] AMDGPU: Avoid default subtarget in hand-written codegen tests (7/9) (PR #205790)

via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Thu Jun 25 05:02:48 PDT 2026 

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

Introduce an -mcpu argument to tests missing it to avoid codegening
the default dummy target. These are cases that didn't require adjusting
the check lines.

Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8)

---

Patch is 74.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/205790.diff


100 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/madmk.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/max-sgprs.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/max3.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/mem-builtins.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/merge-load-store.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/merge-m0.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/min3.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/movrels-bug.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/nullptr.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/operand-spacing.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll (+5-5) 
- (modified) llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/register-count-comments.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/reorder-stores.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/rotl.i64.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/rotr.i64.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/s_movk_i32.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/scratch-buffer.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/sdivrem24.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/select-opt.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/selectcc-opt.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/set-wave-priority.ll (+4-4) 
- (modified) llvm/test/CodeGen/AMDGPU/setcc-opt.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/setcc-sext.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/setcc64.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/sext-in-reg.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/sgprcopies.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/si-spill-cf.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/sint_to_fp.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/smed3.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/spill-before-exec.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/spill-m0.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/store-barrier.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/store-v3i64.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/subreg-intervals.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/subreg_interference.mir (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/target-cpu.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/trap.ll (+18-18) 
- (modified) llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/uint_to_fp.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/umed3.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/undef-build-vector.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/unsupported-calls.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/v_mac.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/verify-sop.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir (+2-2) 


``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
index 9dc44c6e195e4..4fc50b642e299 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn  -run-pass=early-machinelicm -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn  -passes=early-machinelicm -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600  -run-pass=early-machinelicm -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600  -passes=early-machinelicm -o - %s | FileCheck %s
 
 # Test to check machine LICM does not hoist convergent instructions,
 # DS_PERMUTE_B32 in this example.
diff --git a/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll b/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
index 9d0e65bad8244..50347236bb7ae 100644
--- a/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s
 
 ; If the workgroup id range is restricted, we should be able to use
 ; mad24 for the usual indexing pattern.
diff --git a/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir b/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
index 6e7f5b5492148..fcc92dcd23b7c 100644
--- a/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s -debugify-and-strip-all-safe | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s -debugify-and-strip-all-safe | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: bb.0:
 # GCN:  S_MOV_B32 1082130432
diff --git a/llvm/test/CodeGen/AMDGPU/madmk.ll b/llvm/test/CodeGen/AMDGPU/madmk.ll
index 7b96296172035..720b9834ea974 100644
--- a/llvm/test/CodeGen/AMDGPU/madmk.ll
+++ b/llvm/test/CodeGen/AMDGPU/madmk.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
 ; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
 
  ; FIXME: None of these trigger madmk emission anymore. It is still
diff --git a/llvm/test/CodeGen/AMDGPU/max-sgprs.ll b/llvm/test/CodeGen/AMDGPU/max-sgprs.ll
index 429e3cb43328c..b6362a2763811 100644
--- a/llvm/test/CodeGen/AMDGPU/max-sgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/max-sgprs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}max_sgprs_gfx10:
 ; GCN: NumSgprs: 108
diff --git a/llvm/test/CodeGen/AMDGPU/max3.ll b/llvm/test/CodeGen/AMDGPU/max3.ll
index b922854b9c52a..5bbf6c8527a8d 100644
--- a/llvm/test/CodeGen/AMDGPU/max3.ll
+++ b/llvm/test/CodeGen/AMDGPU/max3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=GCN,SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9_1250 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250,GFX9_1250 %s
diff --git a/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll b/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
index 1b3a62628abd6..7d5cb5d48ac6e 100644
--- a/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
+++ b/llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
 
diff --git a/llvm/test/CodeGen/AMDGPU/mem-builtins.ll b/llvm/test/CodeGen/AMDGPU/mem-builtins.ll
index 99090da4da513..ba09608d61446 100644
--- a/llvm/test/CodeGen/AMDGPU/mem-builtins.ll
+++ b/llvm/test/CodeGen/AMDGPU/mem-builtins.ll
@@ -1,5 +1,5 @@
 ; RUN: not llc -mtriple=r600 < %s 2>&1 | FileCheck -check-prefix=ERROR %s
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s
 
 declare hidden i32 @memcmp(ptr addrspace(1) readonly nocapture, ptr addrspace(1) readonly nocapture, i64) #0
 declare hidden ptr addrspace(1) @memchr(ptr addrspace(1) readonly nocapture, i32, i64) #1
diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
index 9c02c935b9498..68e9302ff2a57 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
 
 # Check that SILoadStoreOptimizer honors physregs defs/uses between moved
 # instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir
index d8ee4712a8917..bd2b783d20e52 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
 
 # Check that SILoadStoreOptimizer honors memory dependencies between moved
 # instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/merge-m0.mir b/llvm/test/CodeGen/AMDGPU/merge-m0.mir
index 614ee6762a27b..721e69320dcb3 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-m0.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-m0.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: merge-m0-many-init
 # GCN:    bb.0.entry:
diff --git a/llvm/test/CodeGen/AMDGPU/min3.ll b/llvm/test/CodeGen/AMDGPU/min3.ll
index 82452c861769b..de5527fe24c55 100644
--- a/llvm/test/CodeGen/AMDGPU/min3.ll
+++ b/llvm/test/CodeGen/AMDGPU/min3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=GCN,SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9_1250 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250,GFX9_1250 %s
diff --git a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
index 71c7e32ff23b3..206f5acb5789a 100644
--- a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
+++ b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=prologepilog -o - %s | FileCheck %s
 
 # Make sure the MIR printer doesn't crash when there are dead frame indexes. The
 # CSR SGPR frame indexes are inserted, but deleted.
diff --git a/llvm/test/CodeGen/AMDGPU/movrels-bug.mir b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir
index e20de8c745388..4ec56fbe28024 100644
--- a/llvm/test/CodeGen/AMDGPU/movrels-bug.mir
+++ b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass post-RA-sched  %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn -passes=post-RA-sched  %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass post-RA-sched  %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=post-RA-sched  %s -o - | FileCheck %s
 
 # This tests a situation where a sub-register of a killed super-register operand
 # of V_MOVRELS happens to have an undef use later on. This leads to the post RA
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
index 7e2bfa666a19f..e4e037a17a57b 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 
diff --git a/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir b/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
index d11ef50cbdc8f..03e1b3a0d2caf 100644
--- a/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
+++ b/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn \
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 \
 # RUN:     "-passes=require<amdgpu-resource-usage>,invalidate<amdgpu-resource-usage>" \
 # RUN:     --print-pipeline-passes --filetype=null %s | FileCheck %s
 
diff --git a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
index 60d1df11bfddf..824264dfd61a4 100644
--- a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -O0 -filetype=null < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 -O0 -filetype=null < %s 2>&1 | FileCheck %s
 
 @I = global i32 42
 @P = global ptr @I
diff --git a/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll b/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
index afb289bd28ecf..3de4d29cd21ba 100644
--- a/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
@@ -1,4 +1,4 @@
-; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
 
diff --git a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
index e039225dba3e7..faf4b4077cc47 100644
--- a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
+++ b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
@@ -1,6 +1,6 @@
 ; XFAIL: *
 ; REQUIRES: asserts
-; RUN: llc -mtriple=amdgcn-- < %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s
 
 ; This is a temporary xfail, as the assembly printer is broken when dealing with
 ; lowerConstant() trying to return a value of size greater than 8 bytes.
diff --git a/llvm/test/CodeGen/AMDGPU/nullptr.ll b/llvm/test/CodeGen/AMDGPU/nullptr.ll
index 1552014dc24e0..79c11fb2a7c37 100644
--- a/llvm/test/CodeGen/AMDGPU/nullptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/nullptr.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -mtriple=amdgcn-- | FileCheck -check-prefixes=CHECK,GCN %s
+;RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx600 | FileCheck -check-prefixes=CHECK,GCN %s
 ;RUN: llc < %s -mtriple=r600-- | FileCheck -check-prefixes=CHECK,R600 %s
 
 %struct.S = type { ptr addrspace(5), ptr addrspace(1), ptr addrspace(4), ptr addrspace(3), ptr, ptr addrspace(2)}
diff --git a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
index 1bcddf7d35946..c721b747a5c5a 100644
--- a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
+++ b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-fold-operands -mattr=+dx10-clamp-and-ieee-mode %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-fold-operands -mattr=+dx10-clamp-and-ieee-mode %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
 
diff --git a/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll b/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
index 000d3132171a3..fde295ef61f41 100644
--- a/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=amdgcn | FileCheck --check-prefix=SI %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck --check-prefix=SI %s
 ; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
 
 ; Make sure the OpenCL Image lowering pass doesn't crash when argument metadata
diff --git a/llvm/test/CodeGen/AMDGPU/operand-spacing.ll b/llvm/test/CodeGen/AMDGPU/operand-spacing.ll
index 98d48e505fe6d..96c9f6bec4e69 100644
--- a/llvm/test/CodeGen/AMDGPU/operand-spacing.ll
+++ b/llvm/test/CodeGen/AMDGPU/operand-spacing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
 
 ; Make sure there isn't an extra space between the instruction name and first operands.
diff --git a/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir b/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
index 8adbf284054d6..f8128cbe3e53d 100644
--- a/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass si-optimize-exec-masking-pre-ra -mtriple=amdgcn -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -run-pass si-optimize-exec-masking-pre-ra -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
 ---
 # GCN-LABEL: name: opt_exec_copy_fold
 # GCN:             %2:vreg_64 = COPY $exec
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
index 0d8334cf09606..efe1ca91fb29c 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking -o -  %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-optimize-exec-masking -o -  %s | FileCheck %s
 
 --- |
   define amdgpu_kernel void @optimize_if_and_saveexec_xor(i32 %z, i32 %v) {
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
index e1b41bc868974..549668130236c 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN: name: negated_cond_vop2
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll b/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
index c7b2125862b03..92a8a18a9aede 100644
--- a/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
+++ b/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -verify-coalescing < %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-coalescing < %s
 
 ; The original and requires materializing a 64-bit immediate for
 ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate
diff --git a/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll b/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
index cd6ab0b210844..8cd62abf518fd 100644
--- a/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O3 -mtriple=amdgcn < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -O3 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=CHECK %s
 
 ; SIInsertWaitcnts should preserve waitcnt instructions coming from the user
 
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
index 0a9346326d7d4..1e9a4e83b510b 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=amdgcn -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s
 
 ; Pointer value is stored in a candidate for LDS usage.
 
diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
index bd1752d21507c..d27f45f5813db 100644
--- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
+++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
@@ -1,9 +1,9 @@
-; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s
-; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s
-; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s
 ; RUN: opt -passes=debugify -o %t.bc %s
-; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s
-; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -fi...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/205790

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