[llvm-branch-commits] [llvm] Repurpose MIFlag::NoConvergent (PR #204571)
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llvm-branch-commits at lists.llvm.org
Thu Jun 18 05:20:19 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-testing-tools
Author: Diana Picus (rovka)
<details>
<summary>Changes</summary>
The NoConvergent MIFlag allows us to mark specific instances of
convergent (as indicated by their MCID) MachineInstrs as not convergent.
Sometimes it's useful to do the opposite as well - mark certain
instances of instructions that are not normally convergent as
convergent (for instance inside WWM regions on AMDGPU).
This patch renames the NoConvergent flag to OverrideConvergence. This
can be set to communicate that if the opcode is usually convergent, then
this particular instance of it isn't, and the other way around. When
changing the opcode of an instruction, we first check if the new opcode
has the same "convergence" as the old one - if it does, then we preserve
the flag, otherwise we clear it since we can get the correct convergence
from the opcode now.
Assisted by: Claude Sonnet
---
**Stack**:
- [3/3] #<!-- -->204572
- [2/3] #<!-- -->204571 ⬅
- [1/3] #<!-- -->204570
⚠️ *Part of a stack created by [spr](https://github.com/nhaehnle/spr). Merging this PR using the GitHub UI may have unexpected results.*
---
Patch is 275.83 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/204571.diff
29 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineInstr.h (+43-44)
- (modified) llvm/lib/CodeGen/MIRParser/MILexer.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MIRParser/MILexer.h (+1-1)
- (modified) llvm/lib/CodeGen/MIRParser/MIParser.cpp (+3-3)
- (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+2-2)
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+4-2)
- (modified) llvm/lib/CodeGen/MachineVerifier.cpp (-3)
- (modified) llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll (+92-92)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/call-c-function.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir (+2-2)
- (removed) llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir (-11)
- (renamed) llvm/test/CodeGen/MIR/AMDGPU/overrideconvergence.mir (+5-5)
- (modified) llvm/utils/UpdateTestChecks/mir.py (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index f1f70f019a1b6..b01db218f1901 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -87,47 +87,47 @@ class MachineInstr
enum MIFlag {
NoFlags = 0,
- FrameSetup = 1 << 0, // Instruction is used as a part of
- // function frame setup code.
- FrameDestroy = 1 << 1, // Instruction is used as a part of
- // function frame destruction code.
- BundledPred = 1 << 2, // Instruction has bundled predecessors.
- BundledSucc = 1 << 3, // Instruction has bundled successors.
- FmNoNans = 1 << 4, // Instruction does not support Fast
- // math nan values.
- FmNoInfs = 1 << 5, // Instruction does not support Fast
- // math infinity values.
- FmNsz = 1 << 6, // Instruction is not required to retain
- // signed zero values.
- FmArcp = 1 << 7, // Instruction supports Fast math
- // reciprocal approximations.
- FmContract = 1 << 8, // Instruction supports Fast math
- // contraction operations like fma.
- FmAfn = 1 << 9, // Instruction may map to Fast math
- // intrinsic approximation.
- FmReassoc = 1 << 10, // Instruction supports Fast math
- // reassociation of operand order.
- NoUWrap = 1 << 11, // Instruction supports binary operator
- // no unsigned wrap.
- NoSWrap = 1 << 12, // Instruction supports binary operator
- // no signed wrap.
- IsExact = 1 << 13, // Instruction supports division is
- // known to be exact.
- NoFPExcept = 1 << 14, // Instruction does not raise
- // floatint-point exceptions.
- NoMerge = 1 << 15, // Passes that drop source location info
- // (e.g. branch folding) should skip
- // this instruction.
- Unpredictable = 1 << 16, // Instruction with unpredictable condition.
- NoConvergent = 1 << 17, // Call does not require convergence guarantees.
- NonNeg = 1 << 18, // The operand is non-negative.
- Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
- NoUSWrap = 1 << 20, // Instruction supports geps
- // no unsigned signed wrap.
- SameSign = 1 << 21, // Both operands have the same sign.
- InBounds = 1 << 22, // Pointer arithmetic remains inbounds.
- // Implies NoUSWrap.
- LRSplit = 1 << 23 // Instruction for live range split.
+ FrameSetup = 1 << 0, // Instruction is used as a part of
+ // function frame setup code.
+ FrameDestroy = 1 << 1, // Instruction is used as a part of
+ // function frame destruction code.
+ BundledPred = 1 << 2, // Instruction has bundled predecessors.
+ BundledSucc = 1 << 3, // Instruction has bundled successors.
+ FmNoNans = 1 << 4, // Instruction does not support Fast
+ // math nan values.
+ FmNoInfs = 1 << 5, // Instruction does not support Fast
+ // math infinity values.
+ FmNsz = 1 << 6, // Instruction is not required to retain
+ // signed zero values.
+ FmArcp = 1 << 7, // Instruction supports Fast math
+ // reciprocal approximations.
+ FmContract = 1 << 8, // Instruction supports Fast math
+ // contraction operations like fma.
+ FmAfn = 1 << 9, // Instruction may map to Fast math
+ // intrinsic approximation.
+ FmReassoc = 1 << 10, // Instruction supports Fast math
+ // reassociation of operand order.
+ NoUWrap = 1 << 11, // Instruction supports binary operator
+ // no unsigned wrap.
+ NoSWrap = 1 << 12, // Instruction supports binary operator
+ // no signed wrap.
+ IsExact = 1 << 13, // Instruction supports division is
+ // known to be exact.
+ NoFPExcept = 1 << 14, // Instruction does not raise
+ // floatint-point exceptions.
+ NoMerge = 1 << 15, // Passes that drop source location info
+ // (e.g. branch folding) should skip
+ // this instruction.
+ Unpredictable = 1 << 16, // Instruction with unpredictable condition.
+ OverrideConvergence = 1 << 17, // Flip convergence implied by the opcode.
+ NonNeg = 1 << 18, // The operand is non-negative.
+ Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
+ NoUSWrap = 1 << 20, // Instruction supports geps
+ // no unsigned signed wrap.
+ SameSign = 1 << 21, // Both operands have the same sign.
+ InBounds = 1 << 22, // Pointer arithmetic remains inbounds.
+ // Implies NoUSWrap.
+ LRSplit = 1 << 23 // Instruction for live range split.
};
private:
@@ -1082,9 +1082,8 @@ class MachineInstr
if (ExtraInfo & InlineAsm::Extra_IsConvergent)
return true;
}
- if (getFlag(NoConvergent))
- return false;
- return hasProperty(MCID::Convergent, Type);
+ bool OpcodeConvergent = hasProperty(MCID::Convergent, Type);
+ return getFlag(OverrideConvergence) ? !OpcodeConvergent : OpcodeConvergent;
}
/// Returns true if the specified instruction has a delay slot
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 4188ff8f85131..4a43d5927266e 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -298,7 +298,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("machine-block-address-taken",
MIToken::kw_machine_block_address_taken)
.Case("call-frame-size", MIToken::kw_call_frame_size)
- .Case("noconvergent", MIToken::kw_noconvergent)
+ .Case("override_convergence", MIToken::kw_override_convergence)
.Case("mmra", MIToken::kw_mmra)
.Default(MIToken::Identifier);
}
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 3915222896263..46d5e49d34d67 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -150,7 +150,7 @@ struct MIToken {
kw_ir_block_address_taken,
kw_machine_block_address_taken,
kw_call_frame_size,
- kw_noconvergent,
+ kw_override_convergence,
kw_mmra,
// Metadata types.
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 2924c0dda2390..260eb2e69c887 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1530,7 +1530,7 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
Token.is(MIToken::kw_nsw) ||
Token.is(MIToken::kw_exact) ||
Token.is(MIToken::kw_nofpexcept) ||
- Token.is(MIToken::kw_noconvergent) ||
+ Token.is(MIToken::kw_override_convergence) ||
Token.is(MIToken::kw_unpredictable) ||
Token.is(MIToken::kw_nneg) ||
Token.is(MIToken::kw_disjoint) ||
@@ -1567,8 +1567,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
Flags |= MachineInstr::NoFPExcept;
if (Token.is(MIToken::kw_unpredictable))
Flags |= MachineInstr::Unpredictable;
- if (Token.is(MIToken::kw_noconvergent))
- Flags |= MachineInstr::NoConvergent;
+ if (Token.is(MIToken::kw_override_convergence))
+ Flags |= MachineInstr::OverrideConvergence;
if (Token.is(MIToken::kw_nneg))
Flags |= MachineInstr::NonNeg;
if (Token.is(MIToken::kw_disjoint))
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index b65de01898fd5..8fb49459ac356 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -880,8 +880,8 @@ static void printMI(raw_ostream &OS, MFPrintState &State,
OS << "nomerge ";
if (MI.getFlag(MachineInstr::Unpredictable))
OS << "unpredictable ";
- if (MI.getFlag(MachineInstr::NoConvergent))
- OS << "noconvergent ";
+ if (MI.getFlag(MachineInstr::OverrideConvergence))
+ OS << "override_convergence ";
if (MI.getFlag(MachineInstr::NonNeg))
OS << "nneg ";
if (MI.getFlag(MachineInstr::Disjoint))
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 374c92241b9fb..b228bf81efd0a 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -141,6 +141,8 @@ MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
void MachineInstr::setDesc(const MCInstrDesc &TID) {
if (getParent())
getMF()->handleChangeDesc(*this, TID);
+ if (MCID->isConvergent() != TID.isConvergent())
+ clearFlag(OverrideConvergence);
MCID = &TID;
Opcode = TID.Opcode;
}
@@ -1885,8 +1887,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << "nofpexcept ";
if (getFlag(MachineInstr::NoMerge))
OS << "nomerge ";
- if (getFlag(MachineInstr::NoConvergent))
- OS << "noconvergent ";
+ if (getFlag(MachineInstr::OverrideConvergence))
+ OS << "override_convergence ";
if (getFlag(MachineInstr::NonNeg))
OS << "nneg ";
if (getFlag(MachineInstr::Disjoint))
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b442a65057256..883241ab77c85 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2339,9 +2339,6 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
<< MI->getNumOperands() << " given.\n";
}
- if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent())
- report("NoConvergent flag expected only on convergent instructions.", MI);
-
if (MI->isPHI()) {
if (MF->getProperties().hasNoPHIs())
report("Found PHI instruction with NoPHIs property set", MI);
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 8da255cda656d..48b3418c7ed20 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -1121,7 +1121,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
MI->setFlag(MachineInstr::MIFlag::SameSign);
if (Flags.hasNoConvergent())
- MI->setFlag(MachineInstr::MIFlag::NoConvergent);
+ MI->setFlag(MachineInstr::MIFlag::OverrideConvergence);
}
// Emit all of the actual operands of this instruction, adding them to the
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index ca541c234ba0d..3f05cfb391585 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -1627,7 +1627,7 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MIB.addDef(TRI->getReturnAddressReg(MF));
if (!Info.IsConvergent)
- MIB.setMIFlag(MachineInstr::NoConvergent);
+ MIB.setMIFlag(MachineInstr::OverrideConvergence);
if (!addCallTargetOperands(MIB, MIRBuilder, Info))
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index cd057355b1f1d..9aa73db65a26d 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1457,7 +1457,6 @@ void SIFoldOperandsImpl::foldOperand(
return;
UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
- UseMI->clearFlag(MachineInstr::NoConvergent);
if (OpToFold.isImm()) {
UseMI->getOperand(1).ChangeToImmediate(
@@ -1489,7 +1488,6 @@ void SIFoldOperandsImpl::foldOperand(
UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
UseMI->getOperand(1).setIsKill(false);
UseMI->removeOperand(2); // Remove exec read (or src1 for readlane)
- UseMI->clearFlag(MachineInstr::NoConvergent);
return;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
index edb36079fdfbe..4a6c291623f69 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
@@ -16,7 +16,7 @@ define i64 @load_deref_declaration_only() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @declared_with_ret_deref, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -40,7 +40,7 @@ define i64 @load_deref_unknown_decl() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @unknown_decl
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @unknown_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @unknown_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -64,7 +64,7 @@ define i64 @load_deref_callsite_only() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @unknown_decl
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @unknown_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @unknown_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -89,7 +89,7 @@ define i64 @load_deref_maxmimum_callsite_declaration_only() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @declared_with_ret_deref, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -100,7 +100,7 @@ define i64 @load_deref_maxmimum_callsite_declaration_only() {
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref4
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV1]](p0), @declared_with_ret_deref4, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV1]](p0), @declared_with_ret_deref4, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
@@ -128,7 +128,7 @@ define i64 @load_deref_or_null_declaration_only() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref_or_null
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref_or_null, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @declared_with_ret_deref_or_null, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -152,7 +152,7 @@ define i64 @load_deref_or_null_nonnull_decl() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @nonnull_decl
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @nonnull_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @nonnull_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -176,7 +176,7 @@ define i64 @load_deref_or_null_callsite_only() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @nonnull_decl
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @nonnull_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
+ ; CHECK-NEXT: $sgpr30_sgpr31 = override_convergence G_SI_CALL [[GV]](p0), @nonnull_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
@@ -201,7 +201,7 @@ define i64 @load_deref_or_null_maxmimum_callsite_declaration_only() {
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref_or_null
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)
- ; CH...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/204571
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