[llvm-branch-commits] [llvm] AMDGPU: Refactor AMDGPUTargetID to not store MCSubtargetInfo (PR #204150)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Jun 16 06:31:20 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/204150
Store the triple string and GPUKind instead. The dependence
on checking AMDHSA seems like an anti-feature, but maintain the
behavior of not printing the modifiers for other OSes. Start
parsing the target ID instead of performing a direct string
comparison. Also improve test coverage for the treatment of the
environment component of the triple. The main behavioral change
is this will now produce normalized triples in the output and
diagnostics. Practially, this means all of the places that
currently emit "--" will be expanded into "-unknown-".
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
>From c48ab098dcf3a9c2862c785e798b9f9801ab6d51 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 16 Jun 2026 10:13:54 +0200
Subject: [PATCH] AMDGPU: Refactor AMDGPUTargetID to not store MCSubtargetInfo
Store the triple string and GPUKind instead. The dependence
on checking AMDHSA seems like an anti-feature, but maintain the
behavior of not printing the modifiers for other OSes. Start
parsing the target ID instead of performing a direct string
comparison. Also improve test coverage for the treatment of the
environment component of the triple. The main behavioral change
is this will now produce normalized triples in the output and
diagnostics. Practially, this means all of the places that
currently emit "--" will be expanded into "-unknown-".
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
---
.../llvm/TargetParser/AMDGPUTargetParser.def | 4 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 46 ++++++--
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 105 ++++++++++++------
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 28 ++++-
.../amd-amdgpu-isa-malformed-target-id.s | 5 +
.../amdgcn-target-directive-triple-env.s | 16 +++
.../amdgcn-target-malformed-target-id.s | 5 +
llvm/test/MC/AMDGPU/buffer-op-swz-operand.s | 2 +-
llvm/test/MC/AMDGPU/hsa-diag-v4.s | 10 +-
llvm/test/MC/AMDGPU/hsa-exp.s | 2 +-
llvm/test/MC/AMDGPU/hsa-gfx12-v4.s | 2 +-
llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s | 2 +-
llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s | 2 +-
llvm/test/MC/AMDGPU/hsa-gfx13-v4.s | 2 +-
llvm/test/MC/AMDGPU/hsa-tg-split.s | 2 +-
llvm/test/MC/AMDGPU/hsa-v4.s | 2 +-
.../MC/AMDGPU/hsa-v5-uses-dynamic-stack.s | 2 +-
llvm/test/MC/AMDGPU/isa-version-hsa.s | 8 +-
llvm/test/MC/AMDGPU/isa-version-pal.s | 8 +-
llvm/test/MC/AMDGPU/isa-version-unk.s | 8 +-
llvm/test/MC/AMDGPU/user-sgpr-count.s | 2 +-
21 files changed, 192 insertions(+), 71 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
create mode 100644 llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
create mode 100644 llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
index 191b8e4672082..13946d8aa25c3 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
@@ -123,8 +123,8 @@ AMDGCN_GPU ("gfx1171", GK_GFX1171, (11, 7, 1), FEATURE_FAST_FMA_F32|FEAT
AMDGCN_GPU ("gfx1172", GK_GFX1172, (11, 7, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1200", GK_GFX1200, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1201", GK_GFX1201, (12, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1250", GK_GFX1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS)
-AMDGCN_GPU ("gfx1251", GK_GFX1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS)
+AMDGCN_GPU ("gfx1250", GK_GFX1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx1251", GK_GFX1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS|FEATURE_SRAMECC)
AMDGCN_GPU ("gfx1310", GK_GFX1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
// Generic targets return the lowest common denominator
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 7fe14d8433257..390cd320fd3c3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5980,13 +5980,23 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
if (getParser().parseEscapedString(TargetIDDirective))
return true;
- SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
- if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
- return getParser().Error(TargetRange.Start,
- (Twine(".amdgcn_target directive's target id ") +
- Twine(TargetIDDirective) +
- Twine(" does not match the specified target id ") +
- Twine(getTargetStreamer().getTargetID()->toString())).str());
+ std::optional<AMDGPU::IsaInfo::AMDGPUTargetID> MaybeParsed =
+ AMDGPU::IsaInfo::AMDGPUTargetID::parseTargetIDString(TargetIDDirective);
+ if (!MaybeParsed)
+ return getParser().Error(TargetStart, "malformed target ID");
+
+ const AMDGPU::IsaInfo::AMDGPUTargetID &ParsedTargetID = *MaybeParsed;
+ const std::optional<AMDGPU::IsaInfo::AMDGPUTargetID> &CurrentTargetID =
+ getTargetStreamer().getTargetID();
+
+ if (*CurrentTargetID != ParsedTargetID) {
+ return getParser().Error(
+ TargetStart, (Twine(".amdgcn_target directive's target id ") +
+ Twine(ParsedTargetID.toString()) +
+ Twine(" does not match the specified target id ") +
+ Twine(CurrentTargetID->toString()))
+ .str());
+ }
return false;
}
@@ -6681,9 +6691,25 @@ bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
"architectures");
}
- auto TargetIDDirective = getLexer().getTok().getStringContents();
- if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
- return Error(getParser().getTok().getLoc(), "target id must match options");
+ StringRef TargetIDDirective = getLexer().getTok().getStringContents();
+
+ std::optional<AMDGPU::IsaInfo::AMDGPUTargetID> MaybeParsed =
+ AMDGPU::IsaInfo::AMDGPUTargetID::parseTargetIDString(TargetIDDirective);
+ if (!MaybeParsed)
+ return Error(getParser().getTok().getLoc(), "malformed target id");
+
+ const AMDGPU::IsaInfo::AMDGPUTargetID &ParsedTargetID = *MaybeParsed;
+ const std::optional<AMDGPU::IsaInfo::AMDGPUTargetID> &CurrentTargetID =
+ getTargetStreamer().getTargetID();
+
+ if (*CurrentTargetID != ParsedTargetID) {
+ return Error(getParser().getTok().getLoc(),
+ (Twine(".amd_amdgpu_isa directive's target id ") +
+ Twine(ParsedTargetID.toString()) +
+ Twine(" does not match the specified target id ") +
+ Twine(CurrentTargetID->toString()))
+ .str());
+ }
getTargetStreamer().EmitISAVersion();
Lex();
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 7c283be411b20..697f18752a8d1 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1100,13 +1100,23 @@ VOPD::InstInfo getVOPDInstInfo(unsigned VOPDOpcode,
namespace IsaInfo {
AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI)
- : STI(STI), XnackSetting(TargetIDSetting::Any),
- SramEccSetting(TargetIDSetting::Any) {
- if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
- XnackSetting = TargetIDSetting::Unsupported;
- if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
- SramEccSetting = TargetIDSetting::Unsupported;
-}
+ : Arch(parseArchAMDGCN(STI.getCPU())),
+ TargetTripleString(
+ STI.getTargetTriple().normalize(Triple::CanonicalForm::FOUR_IDENT)),
+ XnackSetting(STI.getFeatureBits().test(FeatureSupportsXNACK)
+ ? TargetIDSetting::Any
+ : TargetIDSetting::Unsupported),
+ SramEccSetting(STI.getFeatureBits().test(FeatureSupportsSRAMECC)
+ ? TargetIDSetting::Any
+ : TargetIDSetting::Unsupported),
+ IsAMDHSA(STI.getTargetTriple().getOS() == Triple::AMDHSA) {}
+
+AMDGPUTargetID::AMDGPUTargetID(GPUKind Arch, StringRef TargetTripleString,
+ TargetIDSetting XnackSetting,
+ TargetIDSetting SramEccSetting, bool IsAMDHSA)
+ : Arch(Arch), TargetTripleString(TargetTripleString),
+ XnackSetting(XnackSetting), SramEccSetting(SramEccSetting),
+ IsAMDHSA(IsAMDHSA) {}
void AMDGPUTargetID::setTargetIDFromFeaturesString(StringRef FS) {
// Check if xnack or sramecc is explicitly enabled or disabled. In the
@@ -1188,40 +1198,67 @@ void AMDGPUTargetID::setTargetIDFromTargetIDStream(StringRef TargetID) {
}
}
-void AMDGPUTargetID::print(raw_ostream &StreamRep) const {
- const Triple &TargetTriple = STI.getTargetTriple();
- auto Version = getIsaVersion(STI.getCPU());
+std::optional<AMDGPUTargetID>
+AMDGPUTargetID::parseTargetIDString(StringRef TargetIDDirective) {
+ // Split on '-' to get arch-vendor-os-environment-processor:features
+ // There is a single dash separator after the 4-component triple
+ SmallVector<StringRef, 5> Parts;
+ TargetIDDirective.split(Parts, '-', /*MaxSplit=*/4);
+ if (Parts.size() < 4)
+ return std::nullopt;
- StreamRep << TargetTriple.getArchName() << '-' << TargetTriple.getVendorName()
- << '-' << TargetTriple.getOSName() << '-'
- << TargetTriple.getEnvironmentName() << '-';
+ Triple TT(Parts[0], Parts[1], Parts[2], Parts[3]);
+ if (!TT.isAMDGCN())
+ return std::nullopt;
- std::string Processor;
- // TODO: Following else statement is present here because we used various
- // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
- // Remove once all aliases are removed from GCNProcessors.td.
- if (Version.Major >= 9)
- Processor = STI.getCPU().str();
- else
- Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
- Twine(Version.Stepping))
- .str();
+ SmallVector<StringRef, 3> FeatureSplit;
+ Parts[4].split(FeatureSplit, ':');
+ if (FeatureSplit.empty())
+ return std::nullopt;
+
+ StringRef CPUName = FeatureSplit[0];
+
+ // Determine xnack/sramecc support based on the architecture attributes
+ GPUKind Arch = parseArchAMDGCN(CPUName);
+ unsigned ArchAttr = getArchAttrAMDGCN(Arch);
- std::string Features;
- if (TargetTriple.getOS() == Triple::AMDHSA) {
+ TargetIDSetting XnackSetting =
+ (ArchAttr & (FEATURE_XNACK | FEATURE_XNACK_ALWAYS))
+ ? TargetIDSetting::Any
+ : TargetIDSetting::Unsupported;
+ TargetIDSetting SramEccSetting = (ArchAttr & FEATURE_SRAMECC)
+ ? TargetIDSetting::Any
+ : TargetIDSetting::Unsupported;
+
+ for (StringRef FeatureString :
+ ArrayRef<StringRef>(FeatureSplit).drop_front(1)) {
+ if (FeatureString.starts_with("xnack"))
+ XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
+ else if (FeatureString.starts_with("sramecc"))
+ SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
+ }
+
+ return AMDGPUTargetID(Arch, TT.normalize(Triple::CanonicalForm::FOUR_IDENT),
+ XnackSetting, SramEccSetting,
+ TT.getOS() == Triple::AMDHSA);
+}
+
+void AMDGPUTargetID::print(raw_ostream &StreamRep) const {
+ StreamRep << TargetTripleString << '-' << getArchNameAMDGCN(Arch);
+
+ if (IsAMDHSA) {
// sramecc.
if (getSramEccSetting() == TargetIDSetting::Off)
- Features += ":sramecc-";
+ StreamRep << ":sramecc-";
else if (getSramEccSetting() == TargetIDSetting::On)
- Features += ":sramecc+";
+ StreamRep << ":sramecc+";
+
// xnack.
if (getXnackSetting() == TargetIDSetting::Off)
- Features += ":xnack-";
+ StreamRep << ":xnack-";
else if (getXnackSetting() == TargetIDSetting::On)
- Features += ":xnack+";
+ StreamRep << ":xnack+";
}
-
- StreamRep << Processor << Features;
}
std::string AMDGPUTargetID::toString() const {
@@ -1231,6 +1268,12 @@ std::string AMDGPUTargetID::toString() const {
return Str;
}
+bool AMDGPUTargetID::operator==(const AMDGPUTargetID &Other) const {
+ return Arch == Other.Arch && XnackSetting == Other.XnackSetting &&
+ SramEccSetting == Other.SramEccSetting && IsAMDHSA == Other.IsAMDHSA &&
+ TargetTripleString == Other.TargetTripleString;
+}
+
unsigned getInstCacheLineSize(const MCSubtargetInfo &STI) {
if (STI.getFeatureBits().test(FeatureInstCacheLineSize128))
return 128;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 6f45f6482ca9a..94b59b24dfe1c 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -16,6 +16,7 @@
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Alignment.h"
+#include "llvm/TargetParser/AMDGPUTargetParser.h"
#include <array>
#include <functional>
#include <utility>
@@ -155,12 +156,19 @@ enum class TargetIDSetting { Unsupported, Any, Off, On };
class AMDGPUTargetID {
private:
- const MCSubtargetInfo &STI;
+ GPUKind Arch;
+ std::string TargetTripleString;
TargetIDSetting XnackSetting;
TargetIDSetting SramEccSetting;
+ bool IsAMDHSA;
public:
explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
+
+ AMDGPUTargetID(GPUKind Arch, StringRef TargetTripleString,
+ TargetIDSetting XnackSetting, TargetIDSetting SramEccSetting,
+ bool IsAMDHSA);
+
~AMDGPUTargetID() = default;
/// \return True if the current xnack setting is not "Unsupported".
@@ -220,11 +228,29 @@ class AMDGPUTargetID {
void setTargetIDFromFeaturesString(StringRef FS);
void setTargetIDFromTargetIDStream(StringRef TargetID);
+ GPUKind getGPUKind() const { return Arch; }
+
+ StringRef getTargetTripleString() const { return TargetTripleString; }
+
+ /// \returns True if this is an AMDHSA target.
+ bool isAMDHSA() const { return IsAMDHSA; }
+
+ /// Parse a target ID directive string (e.g.,
+ /// "amdgcn-amd-amdhsa--gfx1010:xnack-") and return an AMDGPUTargetID.
+ /// \returns AMDGPUTargetID or std::nullopt if malformed.
+ static std::optional<AMDGPUTargetID>
+ parseTargetIDString(StringRef TargetIDDirective);
+
/// Write string representation to \p OS
void print(raw_ostream &OS) const;
/// \returns String representation of an object.
std::string toString() const;
+
+ bool operator==(const AMDGPUTargetID &Other) const;
+ bool operator!=(const AMDGPUTargetID &Other) const {
+ return !(*this == Other);
+ }
};
inline raw_ostream &operator<<(raw_ostream &OS,
diff --git a/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s b/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
new file mode 100644
index 0000000000000..f8a499bfa694f
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx900 %s 2>&1 | FileCheck %s
+
+// Test malformed target ID error handling in .amd_amdgpu_isa directive
+// CHECK: error: malformed target id
+.amd_amdgpu_isa "not-a-valid-target-id"
diff --git a/llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s b/llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
new file mode 100644
index 0000000000000..f3a4e4f8f7b66
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
@@ -0,0 +1,16 @@
+// RUN: split-file %s %t
+// RUN: llvm-mc -triple amdgcn-amd-amdhsa-llvm -mcpu=gfx802 %t/amdhsa-llvm.s | FileCheck --check-prefix=AMDHSA-LLVM %s
+// RUN: llvm-mc -triple amdgcn-amd-amdpal-llvm -mcpu=gfx802 %t/amdpal-llvm.s -filetype=null
+// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx802 %t/amdhsa-llvm.s -filetype=null 2>&1 | FileCheck --check-prefix=AMDHSA-ERR %s
+// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %t/amdpal-llvm.s -filetype=null 2>&1 | FileCheck --check-prefix=AMDPAL-ERR %s
+
+// Test that the environment component of the triple is preserved and validated
+
+//--- amdhsa-llvm.s
+// AMDHSA-LLVM: .amdgcn_target "amdgcn-amd-amdhsa-llvm-gfx802"
+// AMDHSA-ERR: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-llvm-gfx802 does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx802
+.amdgcn_target "amdgcn-amd-amdhsa-llvm-gfx802"
+
+//--- amdpal-llvm.s
+// AMDPAL-ERR: error: .amdgcn_target directive's target id amdgcn-amd-amdpal-llvm-gfx802 does not match the specified target id amdgcn-amd-amdpal-unknown-gfx802
+.amdgcn_target "amdgcn-amd-amdpal-llvm-gfx802"
diff --git a/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s b/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
new file mode 100644
index 0000000000000..3f8c5e7bc24a4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 %s -filetype=null 2>&1 | FileCheck %s
+
+// Test malformed target ID error handling in .amdgcn_target directive
+// CHECK: error: malformed target ID
+.amdgcn_target "not-a-valid-target-id"
diff --git a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
index bf5a30e0f209e..899e136f93735 100644
--- a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
+++ b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
@@ -1,6 +1,6 @@
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1100 --show-inst < %s | FileCheck %s
-// CHECK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
+// CHECK: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1100"
buffer_load_dwordx4 v[0:3], v0, s[0:3], 0, offen offset:4092 slc
// CHECK: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092 slc ; <MCInst #{{[0-9]+}} BUFFER_LOAD_DWORDX4_OFFEN_gfx11
// CHECK-NEXT: ; <MCOperand Reg:VGPR0_VGPR1_VGPR2_VGPR3>
diff --git a/llvm/test/MC/AMDGPU/hsa-diag-v4.s b/llvm/test/MC/AMDGPU/hsa-diag-v4.s
index cdc621ca00733..c4bf7c3e169a4 100644
--- a/llvm/test/MC/AMDGPU/hsa-diag-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-diag-v4.s
@@ -11,11 +11,11 @@
// GCN-LABEL: warning: test_target
// GFX8-NOT: error:
-// GFX10: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa--gfx1010:xnack+
-// GFX11: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa--gfx1100
-// GFX12: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa--[[MCPU]]
-// GFX1170: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa--gfx1170
-// NONAMDHSA: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810:xnack+ does not match the specified target id amdgcn-amd-unknown--gfx810
+// GFX10: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx1010:xnack+
+// GFX11: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx1100
+// GFX12: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa-unknown-[[MCPU]]
+// GFX1170: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx810:xnack+ does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx1170
+// NONAMDHSA: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx810:xnack+ does not match the specified target id amdgcn-amd-unknown-unknown-gfx810
.warning "test_target"
.amdgcn_target "amdgcn-amd-amdhsa--gfx810:xnack+"
diff --git a/llvm/test/MC/AMDGPU/hsa-exp.s b/llvm/test/MC/AMDGPU/hsa-exp.s
index 3cc35b781507b..035b55f8f98bd 100644
--- a/llvm/test/MC/AMDGPU/hsa-exp.s
+++ b/llvm/test/MC/AMDGPU/hsa-exp.s
@@ -14,7 +14,7 @@
// ELF: }
.amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
-// ASM: .amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
+// ASM: .amdgcn_target "amdgcn-unknown-amdhsa-unknown-gfx700"
.amdhsa_code_object_version 4
// ASM: .amdhsa_code_object_version 4
diff --git a/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
index 1ad2510422f76..664db2b8359fd 100644
--- a/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
@@ -49,7 +49,7 @@
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1200"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1200"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1200"
.amdhsa_code_object_version 4
// ASM: .amdhsa_code_object_version 4
diff --git a/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
index 2021bb05c3f15..294f46cbde48f 100644
--- a/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
@@ -65,7 +65,7 @@
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1250"
.p2align 8
.type minimal, at function
diff --git a/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
index 157715b82f3c2..8e1e34651be6c 100644
--- a/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
@@ -65,7 +65,7 @@
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1251"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1251"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1251"
.p2align 8
.type minimal, at function
diff --git a/llvm/test/MC/AMDGPU/hsa-gfx13-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
index 205afbd35a432..b700cec253fb2 100644
--- a/llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
@@ -49,7 +49,7 @@
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1310"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1310"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx1310"
.amdhsa_code_object_version 4
// ASM: .amdhsa_code_object_version 4
diff --git a/llvm/test/MC/AMDGPU/hsa-tg-split.s b/llvm/test/MC/AMDGPU/hsa-tg-split.s
index ca3de214a64a0..bbe72cc7e73e4 100644
--- a/llvm/test/MC/AMDGPU/hsa-tg-split.s
+++ b/llvm/test/MC/AMDGPU/hsa-tg-split.s
@@ -9,7 +9,7 @@
// OBJDUMP-NEXT: 0030 0000ac00 80000000 00000000 00000000
.amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx90a:xnack+"
.amdhsa_code_object_version 4
// ASM: .amdhsa_code_object_version 4
diff --git a/llvm/test/MC/AMDGPU/hsa-v4.s b/llvm/test/MC/AMDGPU/hsa-v4.s
index 931b4e874630b..07e648e3a9982 100644
--- a/llvm/test/MC/AMDGPU/hsa-v4.s
+++ b/llvm/test/MC/AMDGPU/hsa-v4.s
@@ -47,7 +47,7 @@
// OBJDUMP-NEXT: 00f0 0000ac00 80000000 00000000 00000000
.amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx904:xnack+"
.amdhsa_code_object_version 4
// ASM: .amdhsa_code_object_version 4
diff --git a/llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s b/llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
index b71d384b47613..5ee020c0fd132 100644
--- a/llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
+++ b/llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
@@ -52,7 +52,7 @@
// OBJDUMP-NEXT: 00f0 0000ac00 80000000 00000000 00000000
.amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx904:xnack+"
.amdhsa_code_object_version 5
// ASM: .amdhsa_code_object_version 5
diff --git a/llvm/test/MC/AMDGPU/isa-version-hsa.s b/llvm/test/MC/AMDGPU/isa-version-hsa.s
index cdf25501bf7fc..ac7c0e8e46cd5 100644
--- a/llvm/test/MC/AMDGPU/isa-version-hsa.s
+++ b/llvm/test/MC/AMDGPU/isa-version-hsa.s
@@ -8,7 +8,7 @@
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s -filetype=null 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
.amdgcn_target "amdgcn-amd-amdhsa--gfx802"
-// OSABI-HSA: .amdgcn_target "amdgcn-amd-amdhsa--gfx802"
-// OSABI-HSA-ERR: :[[@LINE-2]]:16: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx802 does not match the specified target id amdgcn-amd-amdhsa--gfx803
-// OSABI-PAL-ERR: :[[@LINE-3]]:16: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx802 does not match the specified target id amdgcn-amd-amdpal--gfx802
-// OSABI-UNK-ERR: :[[@LINE-4]]:16: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx802 does not match the specified target id amdgcn-amd-unknown--gfx802
+// OSABI-HSA: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx802"
+// OSABI-HSA-ERR: :[[@LINE-2]]:16: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx802 does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx803
+// OSABI-PAL-ERR: :[[@LINE-3]]:16: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx802 does not match the specified target id amdgcn-amd-amdpal-unknown-gfx802
+// OSABI-UNK-ERR: :[[@LINE-4]]:16: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa-unknown-gfx802 does not match the specified target id amdgcn-amd-unknown-unknown-gfx802
diff --git a/llvm/test/MC/AMDGPU/isa-version-pal.s b/llvm/test/MC/AMDGPU/isa-version-pal.s
index 81f68523b08b2..9c99b3b5936df 100644
--- a/llvm/test/MC/AMDGPU/isa-version-pal.s
+++ b/llvm/test/MC/AMDGPU/isa-version-pal.s
@@ -6,9 +6,9 @@
// RUN: llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s | FileCheck --check-prefix=OSABI-PAL %s
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx803 %s -filetype=null 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
-// OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"
-// OSABI-UNK-ERR: error: target id must match options
-// OSABI-HSA-ERR: error: .amdgcn_target directive's target id amdgcn-amd-amdpal--gfx802 does not match the specified target id amdgcn-amd-amdhsa--gfx802
-// OSABI-PAL-ERR: error: target id must match options
+// OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal-unknown-gfx802"
+// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive's target id amdgcn-amd-amdpal-unknown-gfx802 does not match the specified target id amdgcn-amd-unknown-unknown-gfx802
+// OSABI-HSA-ERR: error: .amdgcn_target directive's target id amdgcn-amd-amdpal-unknown-gfx802 does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx802
+// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive's target id amdgcn-amd-amdpal-unknown-gfx802 does not match the specified target id amdgcn-amd-amdpal-unknown-gfx803
.amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"
.amdgcn_target "amdgcn-amd-amdpal--gfx802"
diff --git a/llvm/test/MC/AMDGPU/isa-version-unk.s b/llvm/test/MC/AMDGPU/isa-version-unk.s
index e34fa1059c311..855dae8a0aa35 100644
--- a/llvm/test/MC/AMDGPU/isa-version-unk.s
+++ b/llvm/test/MC/AMDGPU/isa-version-unk.s
@@ -6,9 +6,9 @@
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s -filetype=null 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s -filetype=null 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
-// OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"
-// OSABI-UNK-ERR: error: target id must match options
-// OSABI-HSA-ERR: error: .amdgcn_target directive's target id amdgcn-amd-unknown--gfx802 does not match the specified target id amdgcn-amd-amdhsa--gfx802
-// OSABI-PAL-ERR: error: target id must match options
+// OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown-unknown-gfx802"
+// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive's target id amdgcn-amd-unknown-unknown-gfx802 does not match the specified target id amdgcn-amd-unknown-unknown-gfx803
+// OSABI-HSA-ERR: error: .amdgcn_target directive's target id amdgcn-amd-unknown-unknown-gfx802 does not match the specified target id amdgcn-amd-amdhsa-unknown-gfx802
+// OSABI-PAL-ERR: error: .amdgcn_target directive's target id amdgcn-amd-unknown-unknown-gfx802 does not match the specified target id amdgcn-amd-amdpal-unknown-gfx802
.amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"
.amdgcn_target "amdgcn-amd-unknown--gfx802"
diff --git a/llvm/test/MC/AMDGPU/user-sgpr-count.s b/llvm/test/MC/AMDGPU/user-sgpr-count.s
index 8a12741920dd4..01458a3ea3e1d 100644
--- a/llvm/test/MC/AMDGPU/user-sgpr-count.s
+++ b/llvm/test/MC/AMDGPU/user-sgpr-count.s
@@ -1,7 +1,7 @@
// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx90a --amdhsa-code-object-version=4 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
.amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa-unknown-gfx90a:xnack+"
// ASM-LABEL: .amdhsa_kernel user_sgprs_implied_count
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