[llvm-branch-commits] [llvm] [AMDGPU] Guard more intrinsics with target features (PR #203956)

[Chinmay Deshpande via llvm-branch-commits]

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@@ -1,7 +1,6 @@
 # RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 %s -o - 2>&1 | FileCheck --check-prefix=ERR %s
 
-# ERR: error: <unknown>:0:0: in function exp0 void (): intrinsic not supported on subtarget
+# Note: gfx11+ rejection of llvm.amdgcn.exp.compr is now enforced at IR translation (see llvm.amdgcn.exp.compr.ll), not during instruction selection.
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chinmaydd wrote:

For this one, I'd guess IR translation since that should mirror SDAG behavior.

Per my understanding, pure subtarget gating of an intrinsic should happen at IR Translation. Failure to select due to operand value/types, immediates, etc. can happen at ISEL (select/legalize)

https://github.com/llvm/llvm-project/pull/203956