[llvm-branch-commits] [llvm] [AArch64] Define GCS operations as SYS and SYSL aliases (PR #203564)

[via llvm-branch-commits]

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@@ -2164,6 +2162,23 @@ class SystemLXtI<bit L, string asm>
   let Inst{7-5}   = op2;
 }
 
+class SystemLXtI<bit L, string asm>
+  : BaseSystemLXtI<L, (outs GPR64:$Rt),
+       (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2), asm>;
+
+// Codegen-only GCS SYSL operations preserve the incoming Rt value when GCS is
+// disabled at runtime, so keep a tied def/use pseudo until asm emission.
+class GCSTiedSystemLXtPseudo
+  : Pseudo<(outs GPR64:$Rt),
+       (ins GPR64:$_Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm,
+            imm0_7:$op2), [], "$Rt = $_Rt">,
+    Sched<[WriteSys]> {
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CarolineConcatto wrote:

Why are we adding this to the scheduler? This was not there before.

https://github.com/llvm/llvm-project/pull/203564