[llvm-branch-commits] [llvm] 3691cf9 - [Test] Fix loop exit conditions to prevent trivial optimizations (#201867)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jun 5 09:27:33 PDT 2026
Author: Timur Golubovich
Date: 2026-06-05T16:19:14Z
New Revision: 3691cf9d025a1d37f69da8abf8577926e8fe9b84
URL: https://github.com/llvm/llvm-project/commit/3691cf9d025a1d37f69da8abf8577926e8fe9b84
DIFF: https://github.com/llvm/llvm-project/commit/3691cf9d025a1d37f69da8abf8577926e8fe9b84.diff
LOG: [Test] Fix loop exit conditions to prevent trivial optimizations (#201867)
Several tests had 'br i1 %ec, label %loop, label %exit' which exits on
the first iteration instead of looping so I swapped them. Also changed
predicates to keep the loops, otherwise they are going to be eliminated
by https://github.com/llvm/llvm-project/pull/201839.
Added:
Modified:
llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
llvm/test/CodeGen/AArch64/pr164181.ll
llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
llvm/test/CodeGen/X86/mbp-false-cfg-break.ll
llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll b/llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
index 1fbca7ca2c27c..8eac8f85126f1 100644
--- a/llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
@@ -43,7 +43,7 @@ define void @fptoui_v8f32_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: fcvtzu.4s v3, v2
; CHECK-NEXT: tbl.16b v1, { v3, v4 }, v0
; CHECK-NEXT: str d1, [x1], #16
-; CHECK-NEXT: b.eq LBB0_1
+; CHECK-NEXT: b.ne LBB0_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
@@ -59,7 +59,7 @@ loop:
store <8 x i8> %c, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -127,7 +127,7 @@ define void @fptoui_2x_v8f32_to_v8i8_in_loop(ptr %A, ptr %B, ptr %dst) {
; CHECK-NEXT: str q1, [x2, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB2_1
+; CHECK-NEXT: b.ne LBB2_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
@@ -147,7 +147,7 @@ loop:
store <16 x i8> %s, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -194,7 +194,7 @@ define void @fptoui_2x_v8f32_to_v8i8_in_loop_no_concat_shuffle(ptr %A, ptr %B, p
; CHECK-NEXT: str q1, [x2, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB3_1
+; CHECK-NEXT: b.ne LBB3_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh5
@@ -214,7 +214,7 @@ loop:
store <16 x i8> %s, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -259,7 +259,7 @@ define void @fptoui_v16f32_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: fcvtzu.4s v3, v7
; CHECK-NEXT: tbl.16b v1, { v3, v4, v5, v6 }, v0
; CHECK-NEXT: str q1, [x1], #32
-; CHECK-NEXT: b.eq LBB4_1
+; CHECK-NEXT: b.ne LBB4_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh7
@@ -275,7 +275,7 @@ loop:
store <16 x i8> %c, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -330,7 +330,7 @@ define void @fptoui_2x_v16f32_to_v16i8_in_loop(ptr %A, ptr %B, ptr %dst) {
; CHECK-NEXT: tbl.16b v1, { v16, v17, v18, v19 }, v0
; CHECK-NEXT: tbl.16b v2, { v20, v21, v22, v23 }, v0
; CHECK-NEXT: stp q2, q1, [x9]
-; CHECK-NEXT: b.eq LBB5_1
+; CHECK-NEXT: b.ne LBB5_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh8, Lloh9
@@ -350,7 +350,7 @@ loop:
store <32 x i8> %s, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -370,7 +370,7 @@ define void @fptoui_v8f32_to_v8i16_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str q0, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB6_1
+; CHECK-NEXT: b.ne LBB6_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
entry:
@@ -385,7 +385,7 @@ loop:
store <8 x i16> %c, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -412,7 +412,7 @@ define void @fptoui_2x_v8f32_to_v8i16_in_loop(ptr %A, ptr %B, ptr %dst) {
; CHECK-NEXT: uzp1.8h v0, v0, v1
; CHECK-NEXT: uzp1.8h v1, v2, v3
; CHECK-NEXT: stp q0, q1, [x9]
-; CHECK-NEXT: b.eq LBB7_1
+; CHECK-NEXT: b.ne LBB7_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
entry:
@@ -431,7 +431,7 @@ loop:
store <16 x i16> %s, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -495,7 +495,7 @@ define void @uitofp_v8i8_to_v8f32(ptr %src, ptr %dst) {
; CHECK-NEXT: ucvtf.4s v3, v3
; CHECK-NEXT: ucvtf.4s v2, v2
; CHECK-NEXT: stp q2, q3, [x9]
-; CHECK-NEXT: b.eq LBB8_1
+; CHECK-NEXT: b.ne LBB8_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh11, Lloh13
@@ -512,7 +512,7 @@ loop:
store <8 x float> %conv, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -623,7 +623,7 @@ define void @uitofp_v16i8_to_v16f32(ptr %src, ptr %dst) {
; CHECK-NEXT: ucvtf.4s v4, v4
; CHECK-NEXT: stp q6, q5, [x9, #32]
; CHECK-NEXT: stp q4, q7, [x9]
-; CHECK-NEXT: b.eq LBB9_1
+; CHECK-NEXT: b.ne LBB9_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh18, Lloh21
@@ -643,7 +643,7 @@ loop:
store <16 x float> %conv, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
diff --git a/llvm/test/CodeGen/AArch64/pr164181.ll b/llvm/test/CodeGen/AArch64/pr164181.ll
index 72b2a77e51c06..7695e3fd61a84 100644
--- a/llvm/test/CodeGen/AArch64/pr164181.ll
+++ b/llvm/test/CodeGen/AArch64/pr164181.ll
@@ -348,10 +348,9 @@ define void @f(i1 %var_0, i16 %var_1, i64 %var_2, i8 %var_3, i16 %var_4, i1 %var
; CHECK-NEXT: .LBB0_35: // %for.inc505.us
; CHECK-NEXT: // in Loop: Header=BB0_36 Depth=5
; CHECK-NEXT: add x22, x22, #1
-; CHECK-NEXT: add x27, x27, #1
+; CHECK-NEXT: adds x27, x27, #1
; CHECK-NEXT: mov w28, wzr
-; CHECK-NEXT: cmp x27, #0
-; CHECK-NEXT: b.hs .LBB0_9
+; CHECK-NEXT: b.ne .LBB0_9
; CHECK-NEXT: .LBB0_36: // %for.body380.us
; CHECK-NEXT: // Parent Loop BB0_4 Depth=1
; CHECK-NEXT: // Parent Loop BB0_6 Depth=2
@@ -466,8 +465,8 @@ if.then466.us: ; preds = %if.then436.us
for.inc505.us: ; preds = %if.then466.us, %if.then436.us, %for.body380.us
%13 = phi i8 [ %11, %for.body380.us ], [ %.sroa.speculated817.us, %if.then466.us ], [ 0, %if.then436.us ]
%indvars.iv.next1019 = add i64 %indvars.iv1018, 1
- %cmp378.us = icmp ult i64 %indvars.iv1018, 0
- br i1 %cmp378.us, label %for.body380.us, label %for.cond510.preheader.us
+ %cmp378.us = icmp ugt i64 %indvars.iv1018, 0
+ br i1 %cmp378.us, label %for.cond510.preheader.us, label %for.body380.us
for.body194.us: ; preds = %if.end.us.7, %for.inc371.us
%indvars.iv = phi i64 [ 0, %if.end.us.7 ], [ %indvars.iv.next, %for.inc371.us ]
diff --git a/llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll b/llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
index 297b25ed075e4..2549405c3b4fe 100644
--- a/llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
@@ -57,7 +57,7 @@ define void @sitofp_v8i8_to_v8f32(ptr %src, ptr %dst) {
; CHECK-NEXT: scvtf v3.4s, v3.4s, #24
; CHECK-NEXT: scvtf v2.4s, v2.4s, #24
; CHECK-NEXT: stp q2, q3, [x9]
-; CHECK-NEXT: b.eq .LBB0_1
+; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
entry:
@@ -72,7 +72,7 @@ loop:
store <8 x float> %conv, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -175,7 +175,7 @@ define void @sitofp_v16i8_to_v16f32(ptr %src, ptr %dst) {
; CHECK-NEXT: scvtf v4.4s, v4.4s, #24
; CHECK-NEXT: stp q6, q5, [x9, #32]
; CHECK-NEXT: stp q4, q7, [x9]
-; CHECK-NEXT: b.eq .LBB1_1
+; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
entry:
@@ -190,7 +190,7 @@ loop:
store <16 x float> %conv, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -215,7 +215,7 @@ define void @sitofp_v8i8_to_v8f16(ptr %src, ptr %dst) {
; CHECK-NEXT: str q1, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq .LBB2_1
+; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
entry:
@@ -230,7 +230,7 @@ loop:
store <8 x half> %conv, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -252,7 +252,7 @@ define void @sitofp_v2i8_to_v2f64(ptr %src, ptr %dst) {
; CHECK-NEXT: str q0, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq .LBB3_1
+; CHECK-NEXT: b.ne .LBB3_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
entry:
@@ -267,7 +267,7 @@ loop:
store <2 x double> %conv, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
diff --git a/llvm/test/CodeGen/AArch64/trunc-to-tbl.ll b/llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
index fd23f3da18cd7..efa2fec519a86 100644
--- a/llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
@@ -57,7 +57,7 @@ define void @trunc_v16i32_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str q1, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB0_1
+; CHECK-NEXT: b.ne LBB0_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
@@ -83,7 +83,7 @@ define void @trunc_v16i32_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: tbl v1.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v0.16b
; CHECK-BE-NEXT: st1 { v1.16b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB0_1
+; CHECK-BE-NEXT: b.ne .LBB0_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -107,7 +107,7 @@ define void @trunc_v16i32_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: uzp1 v2.8h, v3.8h, v2.8h
; CHECK-DISABLE-NEXT: uzp1 v0.16b, v0.16b, v2.16b
; CHECK-DISABLE-NEXT: st1 { v0.16b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB0_1
+; CHECK-DISABLE-NEXT: b.ne .LBB0_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -122,7 +122,7 @@ loop:
store <16 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -230,7 +230,7 @@ define void @trunc_v8i32_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str d1, [x1, x8, lsl #3]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB2_1
+; CHECK-NEXT: b.ne LBB2_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
@@ -252,7 +252,7 @@ define void @trunc_v8i32_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: tbl v1.16b, { v1.16b, v2.16b }, v0.16b
; CHECK-BE-NEXT: st1 { v1.8b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB2_1
+; CHECK-BE-NEXT: b.ne .LBB2_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -271,7 +271,7 @@ define void @trunc_v8i32_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-DISABLE-NEXT: xtn v0.8b, v0.8h
; CHECK-DISABLE-NEXT: st1 { v0.8b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB2_1
+; CHECK-DISABLE-NEXT: b.ne .LBB2_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -286,7 +286,7 @@ loop:
store <8 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -348,7 +348,7 @@ define void @trunc_v16i64_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str q1, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB3_1
+; CHECK-NEXT: b.ne LBB3_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh5
@@ -384,7 +384,7 @@ define void @trunc_v16i64_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: tbl v2.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v0.16b
; CHECK-BE-NEXT: mov v1.d[1], v2.d[0]
; CHECK-BE-NEXT: st1 { v1.16b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB3_1
+; CHECK-BE-NEXT: b.ne .LBB3_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -420,7 +420,7 @@ define void @trunc_v16i64_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: uzp1 v0.8h, v0.8h, v2.8h
; CHECK-DISABLE-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-DISABLE-NEXT: st1 { v0.16b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB3_1
+; CHECK-DISABLE-NEXT: b.ne .LBB3_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -435,7 +435,7 @@ loop:
store <16 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -493,7 +493,7 @@ define void @trunc_v8i64_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str d1, [x1, x8, lsl #3]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB4_1
+; CHECK-NEXT: b.ne LBB4_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh7
@@ -519,7 +519,7 @@ define void @trunc_v8i64_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: tbl v1.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v0.16b
; CHECK-BE-NEXT: st1 { v1.8b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB4_1
+; CHECK-BE-NEXT: b.ne .LBB4_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -544,7 +544,7 @@ define void @trunc_v8i64_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: uzp1 v0.8h, v0.8h, v2.8h
; CHECK-DISABLE-NEXT: xtn v0.8b, v0.8h
; CHECK-DISABLE-NEXT: st1 { v0.8b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB4_1
+; CHECK-DISABLE-NEXT: b.ne .LBB4_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -559,7 +559,7 @@ loop:
store <8 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -596,7 +596,7 @@ define void @trunc_v8i19_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str d0, [x1, x8, lsl #3]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB5_1
+; CHECK-NEXT: b.ne LBB5_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
;
@@ -637,7 +637,7 @@ define void @trunc_v8i19_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-BE-NEXT: xtn v0.8b, v0.8h
; CHECK-BE-NEXT: st1 { v0.8b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB5_1
+; CHECK-BE-NEXT: b.ne .LBB5_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -678,7 +678,7 @@ define void @trunc_v8i19_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-DISABLE-NEXT: xtn v0.8b, v0.8h
; CHECK-DISABLE-NEXT: st1 { v0.8b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB5_1
+; CHECK-DISABLE-NEXT: b.ne .LBB5_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -693,7 +693,7 @@ loop:
store <8 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -724,7 +724,7 @@ define void @trunc_v11i64_to_v11i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: stur b1, [x1, #10]
; CHECK-NEXT: str h2, [x1, #8]
; CHECK-NEXT: add x1, x1, #16
-; CHECK-NEXT: b.eq LBB6_1
+; CHECK-NEXT: b.ne LBB6_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
;
@@ -760,7 +760,7 @@ define void @trunc_v11i64_to_v11i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: stur b0, [x1, #10]
; CHECK-BE-NEXT: str h2, [x1, #8]
; CHECK-BE-NEXT: add x1, x1, #16
-; CHECK-BE-NEXT: b.eq .LBB6_1
+; CHECK-BE-NEXT: b.ne .LBB6_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -796,7 +796,7 @@ define void @trunc_v11i64_to_v11i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: stur b0, [x1, #10]
; CHECK-DISABLE-NEXT: str h2, [x1, #8]
; CHECK-DISABLE-NEXT: add x1, x1, #16
-; CHECK-DISABLE-NEXT: b.eq .LBB6_1
+; CHECK-DISABLE-NEXT: b.ne .LBB6_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -811,7 +811,7 @@ loop:
store <11 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -829,7 +829,7 @@ define void @trunc_v16i16_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str q0, [x1, x8, lsl #4]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB7_1
+; CHECK-NEXT: b.ne LBB7_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
;
@@ -847,7 +847,7 @@ define void @trunc_v16i16_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-BE-NEXT: st1 { v0.16b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB7_1
+; CHECK-BE-NEXT: b.ne .LBB7_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -865,7 +865,7 @@ define void @trunc_v16i16_to_v16i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: cmp x8, #1000
; CHECK-DISABLE-NEXT: uzp1 v0.16b, v0.16b, v1.16b
; CHECK-DISABLE-NEXT: st1 { v0.16b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB7_1
+; CHECK-DISABLE-NEXT: b.ne .LBB7_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -880,7 +880,7 @@ loop:
store <16 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
@@ -897,7 +897,7 @@ define void @trunc_v8i16_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-NEXT: str d0, [x1, x8, lsl #3]
; CHECK-NEXT: add x8, x8, #1
; CHECK-NEXT: cmp x8, #1000
-; CHECK-NEXT: b.eq LBB8_1
+; CHECK-NEXT: b.ne LBB8_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
;
@@ -913,7 +913,7 @@ define void @trunc_v8i16_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-BE-NEXT: cmp x8, #1000
; CHECK-BE-NEXT: xtn v0.8b, v0.8h
; CHECK-BE-NEXT: st1 { v0.8b }, [x9]
-; CHECK-BE-NEXT: b.eq .LBB8_1
+; CHECK-BE-NEXT: b.ne .LBB8_1
; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret
;
@@ -929,7 +929,7 @@ define void @trunc_v8i16_to_v8i8_in_loop(ptr %A, ptr %dst) {
; CHECK-DISABLE-NEXT: cmp x8, #1000
; CHECK-DISABLE-NEXT: xtn v0.8b, v0.8h
; CHECK-DISABLE-NEXT: st1 { v0.8b }, [x9]
-; CHECK-DISABLE-NEXT: b.eq .LBB8_1
+; CHECK-DISABLE-NEXT: b.ne .LBB8_1
; CHECK-DISABLE-NEXT: // %bb.2: // %exit
; CHECK-DISABLE-NEXT: ret
entry:
@@ -944,7 +944,7 @@ loop:
store <8 x i8> %trunc, ptr %gep.dst
%iv.next = add i64 %iv, 1
%ec = icmp eq i64 %iv.next, 1000
- br i1 %ec, label %loop, label %exit
+ br i1 %ec, label %exit, label %loop
exit:
ret void
diff --git a/llvm/test/CodeGen/X86/mbp-false-cfg-break.ll b/llvm/test/CodeGen/X86/mbp-false-cfg-break.ll
index fc2549153321e..aeb558dbd5eaa 100644
--- a/llvm/test/CodeGen/X86/mbp-false-cfg-break.ll
+++ b/llvm/test/CodeGen/X86/mbp-false-cfg-break.ll
@@ -28,7 +28,7 @@ backedge:
call void @foo()
%iv.next = add i32 %iv, 1
%cmp = icmp eq i32 %iv.next, 200
- br i1 %cmp, label %loop, label %exit, !prof !{!"branch_weights", i32 1000, i32 1}
+ br i1 %cmp, label %exit, label %loop, !prof !{!"branch_weights", i32 1, i32 1000}
exit:
ret void
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
index e6ee9b467c5e0..8abd0b977ba05 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll
@@ -83,7 +83,7 @@ define void @pr63840_crash(i64 %sext974, i64 %sext982, i8 %x) {
; CHECK-NEXT: [[PHI1094]] = phi i64 [ [[LSR_IV_NEXT8_LCSSA]], [[BB992]] ], [ [[ADD1054]], [[BB1059]] ]
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 1
; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i64 [[LSR_IV3]], [[SEXT1046]]
-; CHECK-NEXT: [[ICMP1050:%.*]] = icmp ult i64 [[LSR_IV_NEXT]], 0
+; CHECK-NEXT: [[ICMP1050:%.*]] = icmp ugt i64 [[LSR_IV_NEXT]], 0
; CHECK-NEXT: br i1 [[ICMP1050]], label [[BB1053:%.*]], label [[BB1051:%.*]]
;
bb:
@@ -120,6 +120,6 @@ bb1064: ; preds = %bb1059, %bb1053
bb1092: ; preds = %bb1059, %bb992
%phi1093 = phi i64 [ 0, %bb992 ], [ %add1060, %bb1059 ]
%phi1094 = phi i64 [ %add1047, %bb992 ], [ %add1054, %bb1059 ]
- %icmp1050 = icmp ult i64 %phi1093, 0
+ %icmp1050 = icmp ugt i64 %phi1093, 0
br i1 %icmp1050, label %bb1053, label %bb1051
}
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