[llvm-branch-commits] [llvm] [LoopInterchange] Bail out if function that may diverge is called (PR #201348)
Ryotaro Kasuga via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jun 3 05:52:37 PDT 2026
https://github.com/kasuga-fj created https://github.com/llvm/llvm-project/pull/201348
None
>From 036babe1b4950eb0050f346a1a5adb7e1fd9d56f Mon Sep 17 00:00:00 2001
From: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: Wed, 3 Jun 2026 12:46:33 +0000
Subject: [PATCH] [LoopInterchange] Bail out if function that may diverge is
called
---
.../lib/Transforms/Scalar/LoopInterchange.cpp | 6 +-
.../LoopInterchange/function-attr.ll | 56 ++++++-------------
2 files changed, 20 insertions(+), 42 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
index 707d44c8411e8..df46a37be655a 100644
--- a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
@@ -1474,8 +1474,10 @@ bool LoopInterchangeLegality::canInterchangeLoops(unsigned InnerLoopId,
for (auto *BB : OuterLoop->blocks())
for (Instruction &I : *BB)
if (CallInst *CI = dyn_cast<CallInst>(&I)) {
- // Functions which don't access memory do not prevent interchanging.
- if (CI->doesNotAccessMemory() || isa<PseudoProbeInst>(CI))
+ // Functions which don't access memory and doesn't diverge do not
+ // prevent interchanging.
+ if ((CI->doesNotAccessMemory() && !CI->mayHaveSideEffects()) ||
+ isa<PseudoProbeInst>(CI))
continue;
LLVM_DEBUG(
dbgs() << "Loops with call instructions cannot be interchanged "
diff --git a/llvm/test/Transforms/LoopInterchange/function-attr.ll b/llvm/test/Transforms/LoopInterchange/function-attr.ll
index a26d308b4eb6b..6642047ce5598 100644
--- a/llvm/test/Transforms/LoopInterchange/function-attr.ll
+++ b/llvm/test/Transforms/LoopInterchange/function-attr.ll
@@ -134,43 +134,31 @@ exit:
; Interchanging the loops changes the semantics of the program, e.g., `A[0][9]`
; will be overwritten in the original code, but not in the interchanged one.
;
-; FIXME: Currently the loops are interchanged.
-;
define void @call_throw_exception(ptr %A) {
; CHECK-LABEL: define void @call_throw_exception(
; CHECK-SAME: ptr [[A:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: br label %[[INNER_HEADER_PREHEADER:.*]]
-; CHECK: [[OUTER_HEADER_PREHEADER:.*]]:
-; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
-; CHECK: [[OUTER_HEADER]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[OUTER_HEADER_PREHEADER]] ]
-; CHECK-NEXT: br label %[[INNER_HEADER_SPLIT:.*]]
-; CHECK: [[INNER_HEADER_PREHEADER]]:
+; CHECK-NEXT: [[INNER_HEADER_PREHEADER:.*]]:
; CHECK-NEXT: br label %[[INNER_HEADER:.*]]
; CHECK: [[INNER_HEADER]]:
-; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[TMP0:%.*]], %[[INNER_LATCH_SPLIT:.*]] ], [ 0, %[[INNER_HEADER_PREHEADER]] ]
-; CHECK-NEXT: br label %[[OUTER_HEADER_PREHEADER]]
-; CHECK: [[INNER_HEADER_SPLIT]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[INNER_HEADER_PREHEADER]] ], [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
+; CHECK-NEXT: br label %[[OUTER_HEADER_PREHEADER:.*]]
+; CHECK: [[OUTER_HEADER_PREHEADER]]:
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[INNER_HEADER]] ], [ [[TMP0:%.*]], %[[INNER_LATCH:.*]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr [10 x i8], ptr [[A]], i64 [[J]], i64 [[I]]
; CHECK-NEXT: store i8 0, ptr [[GEP]], align 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[J]], 1
-; CHECK-NEXT: br i1 [[COND]], label %[[UNWIND:.*]], label %[[INNER_LATCH:.*]]
+; CHECK-NEXT: br i1 [[COND]], label %[[UNWIND:.*]], label %[[INNER_LATCH]]
; CHECK: [[UNWIND]]:
; CHECK-NEXT: call void @throw_exception()
; CHECK-NEXT: br label %[[INNER_LATCH]]
; CHECK: [[INNER_LATCH]]:
-; CHECK-NEXT: [[J_NEXT:%.*]] = add i64 [[J]], 1
-; CHECK-NEXT: [[EC_INNER:%.*]] = icmp eq i64 [[J_NEXT]], 10
-; CHECK-NEXT: br label %[[OUTER_LATCH]]
-; CHECK: [[INNER_LATCH_SPLIT]]:
; CHECK-NEXT: [[TMP0]] = add i64 [[J]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 10
-; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNER_HEADER]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[OUTER_LATCH]], label %[[OUTER_HEADER_PREHEADER]]
; CHECK: [[OUTER_LATCH]]:
; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
; CHECK-NEXT: [[EC_OUTER:%.*]] = icmp eq i64 [[I_NEXT]], 10
-; CHECK-NEXT: br i1 [[EC_OUTER]], label %[[INNER_LATCH_SPLIT]], label %[[OUTER_HEADER]]
+; CHECK-NEXT: br i1 [[EC_OUTER]], label %[[EXIT:.*]], label %[[INNER_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
@@ -219,42 +207,30 @@ exit:
; present in the original code (e.g., `A[9999]`) which results in UB. Thus we
; cannot interchange the loops.
;
-; FIXEM: Currently the loops are deemed legal to interchange.
-;
define void @call_not_return() {
; CHECK-LABEL: define void @call_not_return() {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
-; CHECK: [[OUTER_HEADER_PREHEADER:.*]]:
-; CHECK-NEXT: br label %[[INNER_HEADER:.*]]
-; CHECK: [[INNER_HEADER]]:
-; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[OUTER_HEADER_PREHEADER]] ]
-; CHECK-NEXT: br label %[[INNER_HEADER_SPLIT:.*]]
-; CHECK: [[OUTER_HEADER]]:
+; CHECK-NEXT: [[OUTER_HEADER:.*]]:
; CHECK-NEXT: br label %[[INNER_HEADER1:.*]]
; CHECK: [[INNER_HEADER1]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[TMP0:%.*]], %[[INNER_LATCH_SPLIT:.*]] ], [ 0, %[[OUTER_HEADER]] ]
-; CHECK-NEXT: br label %[[OUTER_HEADER_PREHEADER]]
-; CHECK: [[INNER_HEADER_SPLIT]]:
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
+; CHECK-NEXT: br label %[[OUTER_HEADER_PREHEADER:.*]]
+; CHECK: [[OUTER_HEADER_PREHEADER]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[INNER_HEADER1]] ], [ [[TMP0:%.*]], %[[INNER_LATCH:.*]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr [10 x i8], ptr @ARR_100, i64 [[J]], i64 [[I]]
; CHECK-NEXT: store i8 0, ptr [[GEP]], align 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[I]], 1
-; CHECK-NEXT: br i1 [[COND]], label %[[TRAP:.*]], label %[[INNER_LATCH:.*]]
+; CHECK-NEXT: br i1 [[COND]], label %[[TRAP:.*]], label %[[INNER_LATCH]]
; CHECK: [[TRAP]]:
; CHECK-NEXT: call void @not_return()
; CHECK-NEXT: br label %[[INNER_LATCH]]
; CHECK: [[INNER_LATCH]]:
-; CHECK-NEXT: [[J_NEXT:%.*]] = add i64 [[I]], 1
-; CHECK-NEXT: [[EC_INNER:%.*]] = icmp eq i64 [[J_NEXT]], 10
-; CHECK-NEXT: br label %[[OUTER_LATCH]]
-; CHECK: [[INNER_LATCH_SPLIT]]:
; CHECK-NEXT: [[TMP0]] = add i64 [[I]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 10
-; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNER_HEADER1]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[OUTER_LATCH]], label %[[OUTER_HEADER_PREHEADER]]
; CHECK: [[OUTER_LATCH]]:
; CHECK-NEXT: [[I_NEXT]] = add i64 [[J]], 1
; CHECK-NEXT: [[EC_OUTER:%.*]] = icmp eq i64 [[I_NEXT]], 1000
-; CHECK-NEXT: br i1 [[EC_OUTER]], label %[[INNER_LATCH_SPLIT]], label %[[INNER_HEADER]]
+; CHECK-NEXT: br i1 [[EC_OUTER]], label %[[EXIT:.*]], label %[[INNER_HEADER1]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
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