[llvm-branch-commits] [llvm] [RISCV] Support CodeGen of Zilx extension (PR #209420)

[Craig Topper via llvm-branch-commits]

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@@ -671,7 +671,8 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
       return false;
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topperc wrote:

I think we need to add IsSignExtendingOpW = 1 to the byte, halfword, and signed load instructions. Unless you want to do that in a different patch.

https://github.com/llvm/llvm-project/pull/209420